HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 870

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Rev. 2.00 Feb. 12, 2010 Page 786 of 1330
REJ09B0554-0200
Legend:
CANTCNTR
CANTCR
CANTCMR
CANMCR
CANGSR
CANIRR
CANIMR
CANBCR
CANREC
Note: Since the HCAN2 is designed on the basis of a 16-bit bus system, longword (32-bit) accesses are prohibited.
Data-out[15:0]
Address[10:0]
Data-in[15:0]
Interrupt
Reset
Clock
Wait
All registers can be accessed with words and mailboxes can be accessed with words or bytes.
CAN Interface
: Timer counter register
: Timer control register
: Timer compare match register
: Master control register
: General status register
: Interrupt request register
: Interrupt mask register
: Bit configuration register
: Receive error counter
CANBCR
CANTCNTR
CANMCR
CANGSR
CANTCR
Figure 22.1 Block Diagram of HCAN2 Module
CPU interface
16-bit timer
CANREC
CAN Rx
CANTCMR
Transmit buffer
CANIMR
CANIRR
CAN Tx
Can core
CANTEC
CANTXPR
CANTXCR
CANTXACK
CANABACK
CANRXPR
CANRFPR
CANMBIMR
CANUMSR
Receive buffer
Mailbox0
Mailbox1
Mailbox2
Mailbox3
Mailbox4
Mailbox5
Mailbox6
Mailbox7
CANMBIMR
CANTXPR
CANRXPR
CANTXCR
: Transmit error counter
: Transmit pending request register
: Transmit cancel register
: Transmit acknowledge register
: Abort acknowledge register
: Receive data frame pending register
: Remote frame request pending register
: Mailbox interrupt mask register
: Unread message status register
Mailbox8
Mailbox9
Mailbox10
Mailbox11
Mailbox12
Mailbox13
Mailbox14
Mailbox15
These registers are doubled
Mailbox0-31 (RAM)
Mailbox control
Control
signals
CANTEC
CAN_NERR
Mailbox16
Mailbox17
Mailbox18
Mailbox19
Mailbox20
Mailbox21
Mailbox22
Mailbox23
CANTXACK
CANABACK
CANUMSR
CANRFPR
Status
signals
CAN bus
Mailbox24
Mailbox25
Mailbox26
Mailbox27
Mailbox28
Mailbox29
Mailbox30
Mailbox31