HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 31

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Item
30.3 Register
Configuration
Table 30.2 Register
Configuration (1)
30.3.10 LCDC
Horizontal Character
Number Register
(LDHCNR)
30.3.17 LCDC Power
Management Mode
Register (LDPMMR)
30.4.6 Power Supply
Control Sequence
Processing
Figure 30.4 Power-
Supply Control
Sequence and States of
the LCD Module
Figure 30.5 Power-
Supply Control
Sequence and States of
the LCD Module
Figure 30.6 Power-
Supply Control
Sequence and States of
the LCD Module
Figure 30.7 Power-
Supply Control
Sequence and States of
the LCD Module
30.6 Usage Notes
32.2 Register Bits
Page
1080
1088
1099
1100
1117
1178
Revision (See Manual for Details)
Notes added
Notes: 1. There are 256 registers: LDPR00, LDPR01, ……,
Note amended
Note: The values set in HDCN and HTCN must satisfy the
Table amended
Figure amended
Figure amended
(out) Display data,
Figure amended
Figure amended
Newly added
Table amended
Abbrev.
SCRER0
Bit
4
(out) Display data,
(out) Display data,
(out) Display data,
timing signal
timing signal
timing signal
timing signal
relationship of HTCN ≥ HDCN + 3.
Bit Name
DONE
2. Modification During Display - Yes: Modification
Bit 31/
23/15/7
⎯
⎯
LDPRFF. These registers are allocated to H'FE30
0800, H'FE30 0804, ……, H'FE30 0BFC.
during display on the LCD allowed, No: Modification
during display on the LCD not allowed.
Low
Low
Low
Low
Bit 30/
22/14/6
PER6
FER6
Initial Value
1
Undefined
Bit 29/
21/13/5
PER5
FER5
Rev. 2.00 Feb. 12, 2010 Page xxix of lxxxii
R/W
R/W
Bit 28/
20/12/4
PER4
FER4
Arbitrary
Description
LCD_DON Pin Enable
Sets whether or not to enable a power-supply
control sequence using the LCD_DON pin.
0: Disabled: LCD_DON pin output is masked and
1: Enabled: LCD_DON pin output is asserted and
fixed low
negated according to the power-on or power-off
sequence
Bit 27/
19/11/3
PER3
FER3
Arbitrary
Arbitrary
Arbitrary
Bit 26/
18/10/2
PER2
FER2
Bit 25/
17/9/ 1
PER1
FER1
REJ09B0554-0200
Low
Bit 24/
16/8/0
PER0
FER0
Undefined
Low
Module
Low
Low