HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 938

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

23.3.2
SPSR is a 32-bit readable/writable register. The status flag in SPSR can confirm whether the
system correctly operates or not. If the ROIE bit in SPSCR is set to 1, an interrupt request is
generated due to the occurrence of the receive buffer overrun error or the warning of the receive
buffer overrun error. When the TFIE bit in SPSCR is set to 1, an interrupt request is generated by
the transmit complete status flag. If the appropriate enable bit in SPSCR is set to 1, an interrupt
request is generated due to the receive FIFO halfway, receive FIFO full, transmit FIFO empty, or
transmit FIFO halfway flag. If the RNIE bit in SPSCR is set to 1, an interrupt request is generated
when the receive FIFO is not empty.
Initial value:
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 854 of 1330
REJ09B0554-0200
Bit
31 to 11 ⎯
10
9
R/W:
R/W:
Bit:
Bit:
Status Register (SPSR)
Bit Name
TXFU
TXHA
31
15
R
R
-
-
-
-
30
14
R
R
-
-
-
-
29
13
R
R
-
-
-
-
Initial Value
All ⎯
0
0
28
12
R
R
-
-
-
-
27
11
R
R
-
-
-
-
TXFU TXHA TXEM
R/W
R
R
R
26
10
R
R
0
-
-
25
R
R
9
0
-
-
Description
Reserved
These bits are always read as an undefined
value. The write value should always be 0.
This status flag is enabled only to operation in
FIFO mode. The flag is set to 1 when the transmit
FIFO is full of bytes for transmission and cannot
accept any more. It is cleared to 0 when data is
transmitted from the transmit FIFO.
This status flag is enabled only to operation in
FIFO mode. The flag is set to 1 when the transmit
FIFO reaches the halfway point, that is, it has 4
bytes of data and 4 spaces for more data. It is
cleared to 0 when more data is written to the
transmit FIFO. It remains set to 1 until cleared to 0
regardless of the subsequent FIFO levels.
If TXHA = 1 and THIE = 1 then the interrupt is
generated.
Transmit FIFO Full Flag
Transmit FIFO Halfway Flag
24
R
R
8
1
-
-
RXFU RXHA RXEM
23
R
R
7
0
-
-
22
R
R
6
0
-
-
21
R
R
5
1
-
-
RXOO RXOW RXFL TXFN TXFL
R/W* R/W*
20
R
4
0
-
-
19
R
3
0
-
-
18
R
R
2
0
-
-
17
R
R
1
0
-
-
16
R
R
0
0
-
-