HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 604

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

(2) Exit from Software Standby Mode
Software standby mode is exited by means of an interrupt (NMI, IRL, IRQ*, or GPIO) or a reset
via the RESET and MRESET pins.
Note: * Software standby mode can be cleared by an IRQ4 or IRQ5 interrupt, but not by an
(a) Exit by interrupt
(b) Exit by reset
(3) Clock Pause Function
In software standby mode, it is possible to stop or change the frequency of the clock input from
the EXTAL pin. This function is used as follows.
(a) Enter software standby mode following the transition procedure described above.
(b) When software standby mode is entered and the LSI's internal clock stops, a low-level signal is
(c) The input clock is stopped, or its frequency changed, after the STATUS1 pin goes low and the
(d) When the frequency is changed, input an NMI interrupt after the change. When the clock is
(e) After the time set in the WDT, clock supply begins inside the LSI, the STATUS1 and
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A hot start can be performed by means of the on-chip WDT. When an NMI, IRL, IRQ, or
GPIO interrupt is detected, the WDT starts counting. After the count overflows, clocks are
supplied to the entire LSI, software standby mode is exited, and the STATUS1 and STATUS0
pins both go low. Interrupt exception handling is then executed, and the code corresponding to
the interrupt source is set in INTEVT. In standby mode, interrupts are accepted even if the BL
bit in the SR register is 1, and so, if necessary, SPC and SSR should be saved to the stack
before executing the SLEEP instruction.
The phase of the CKIO pin clock output may be unstable immediately after an interrupt is
detected, until software standby mode is exited.
Software standby mode is exited by means of a reset (power-on or manual) via the RESET pin.
The RESET pin should be held low until clock oscillation stabilizes. The internal clock
continues to be output at the CKIO pin.
output at the STATUS1 pin, and a high-level signal at the STATUS0 pin.
STATUS0 pin high.
stopped, input an NMI interrupt after applying the clock.
STATUS0 pins both go low, and operation is resumed from interrupt exception handling.
IRQ6 or IRQ7 interrupt.