HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 897

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

22.5.3
The CANBCR registers are 16-bit read/write registers that is used to set CAN bit timing
parameters and the baud rate pre-scaler for the CAN interface.
For the following description, the timequanta is defined as follows:
Where: BRP (Baud Rate Predivider) is a value stored in CANBCR0 and f
frequency.
• CANBCR1
Initial value:
Bit
2
1
0
R/W:
Bit:
Timequanta =
TSEG1
Bit Name
GSR2
GSR1
GSR0
Bit Configuration Registers 1 and 0 (CANBCR1, CANBCR0)
R/W
_3
15
0
TSEG1
R/W
_2
14
0
TSEG1
R/W
13
_1
0
Initial Value
1
0
0
BRP
f
clk
TSEG1
R/W
12
_0
0
11
R
0
-
TSEG2
R/W
R/W
R
R
R
10
_2
0
TSEG2
R/W
_1
9
0
Description
Message Transmission Complete Flag
Flag that indicates to the host CPU if HCAN2 is
processing transmission requests or a
transmission is completed. This bit is an OR'ed
signal of all the CANTXPR bits. Please note the
difference to the meaning of IRR8 (Slot Empty)
that is an OR'ed signal of all the
CANTXACK/CANABACK bits.
0: Transmission in progress
1: There is no message requested for
Transmit/Receive Warning Flag
Flag that indicates an error warning.
0: Clearing condition: TEC < 96 or REC < 96 or
1: Setting condition: 96 < TEC < 256 or 96 < REC
Bus Off Flag
Flag that indicates that the HCAN2 is in the Bus
Off state.
0: Clearing condition: Recovery from the
1: Setting condition: TEC ≥ 256 (Bus Off state)
TSEG2
R/W
_0
8
0
transmission.
TEC ≥ 256
< 256
Bus Off State
R
7
0
-
Rev. 2.00 Feb. 12, 2010 Page 813 of 1330
R
0
6
-
SJW1 SJW0
R/W
5
0
R/W
4
0
clk
is the peripheral clock
R
3
0
-
REJ09B0554-0200
R
0
2
-
R/W
EG
1
0
BSP
R/W
0
0