HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 151

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

4.1
PC: At the start of instruction execution, the PC indicates the address of the instruction itself.
• Data sizes and data types
Load-Store Architecture: The SH-4 has a load-store architecture in which operations are
basically executed using registers. Except for bit-manipulation operations such as logical AND
that are executed directly in memory, operands in an operation that requires memory access are
loaded into registers and the operation is executed between the registers.
Delayed Branches: Except for the two branch instructions BF and BT, the SH-4 branch
instructions and RTE are delayed branches. In a delayed branch, the instruction following the
branch is executed before the branch destination instruction. This execution slot following a
delayed branch is called a delay slot. For example, the BRA execution sequence is as follows:
Static Sequence
BRA
ADD R1, R0
next_2
Delay Slot: A slot illegal instruction exception may occur when a specific instruction is executed
in a delay slot. For details, see section 8, Exceptions. The instruction following BF/S or BT/S for
which the branch is not taken is also a delay slot instruction.
T Bit: The T bit in SR is used to show the result of a compare operation, and is referenced by a
conditional branch instruction. An example of the use of a conditional branch instruction is shown
below.
The SH-4 instruction set is implemented with 16-bit fixed-length instructions. The SH-4 can
use byte (8-bit), word (16-bit), longword (32-bit), and quadword (64-bit) data sizes for
memory access. Single-precision floating-point data (32 bits) can be moved to and from
memory using longword or quadword size. Double-precision floating-point data (64 bits) can
be moved to and from memory using longword size. When a double-precision floating-point
operation is specified (PR in FPSCR = 1), the result of an operation using quadword access
will be undefined. When the SH-4 moves byte-size or word-size data from memory to a
register, the data is sign-extended.
TARGET
Execution Environment
Dynamic Sequence
BRA TARGET
ADD R1, R0
target_instr
Section 4 Instruction Set
ADD in delay slot is executed before
branching to TARGET
Rev. 2.00 Feb. 12, 2010 Page 67 of 1330
REJ09B0554-0200