HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1066

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

(6) Commands with Write Data
Flash memory operation commands include a number of commands involving write data. Such
commands confirm the card status by the command argument and command response, and
transmit card information and flash memory data via the MCDAT pin. For a command that is
related to time-consuming processing such as flash memory write, the card indicates the data busy
state via the MCDAT pin.
The number of bytes of flash memory to be written is specified by CMD16 as a block size, or if
not specified, writing is continued until it is aborted by CMD12 during multiblock or stream
transfer. In multiblock transfer, the transfer operation is suspended for every block and an
instruction to continue or end the command sequence is waited for.
The suspension of the command sequence depends on the size of the block and FIFO. The
command sequence ends without suspending the data transfer when block size ≤ FIFO size. When
block size > FIFO size, the command sequence is suspended by FIFO empty. Once the command
sequence is suspended, the next data is written to the FIFO before the command sequence is
continued. In multiblock transfer, the command sequence is suspended for every block.
Figures 26.15 to 26.18 show examples of the command sequence for commands with write data.
Figures 26.19 to 26.21 show the operational flows for commands with write data.
• Make settings to issue a command, and set write data to FIFO.
• Set the START bit in CMDSTRT to 1 to start command transmission. MCCMD must be kept
• Command transmission completion can be confirmed by the command transmit end interrupt
• The command response is received from the card.
• If the card returns no command response, the command response is detected by the command
• Set the DATAEN bit in OPCR to 1 to start write data transmission. MCDAT must be kept
• Inter-block suspension in multiblock transfer and suspension according to the FIFO empty are
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driven until the end bit output is completed.
(CMDI).
timeout error (CTERI).
driven until the end bit output is completed.
detected by the data transfer end interrupt (DTI), data response interrupt (DRPI), and FIFO
empty interrupt (FEI), respectively. In addition, after the end of data transfer (DRPI detection),
the data busy state is checked through DTBUSY in CSTR. If the card is in data busy state,
cancellation of the data busy state is detected by the data busy end interrupt (DBSYI).
To continue the command sequence, write data should be written to the FIFO, and the
DATAEN bit in OPCR should be set to 1. To end the command sequence, the CMDOFF bit in
OPCR should be set to 1, and the CMD12 should be issued.