HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 546

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

(1) Conditions for Ending Transfer on Individual Channels
Transfer ends on the corresponding channel when either of the following conditions is satisfied:
• The DMATCR value reaches 0.
• The DE bit in CHCR is cleared to 0.
(2) Conditions for Ending Transfer Simultaneously on All Channels
Transfer ends on all channels simultaneously when either of the following conditions is satisfied:
• The AE or NMIF bit in DMAOR is set to 1.
• The DME bit in DMAOR is cleared to 0.
Rev. 2.00 Feb. 12, 2010 Page 462 of 1330
REJ09B0554-0200
1. End of transfer when DMATCR = 0
2. End of transfer when DE = 0 in CHCR
1. End of transfer with DMAOR.AE = 1
When the DMATCR value reaches 0, the DMAC terminates DMA transfer on the
corresponding channel and sets the TE bit in CHCR. If the IE bit is set at this time, an
interrupt (DMTE) request is sent to the CPU (an interrupt (DMTE) request can not be sent
to the CPU for a DMA transfer end when DMATCR = 0 in a DMABRG request).
Transfer ending with DMATCR = 0 does not follow the procedures described in 1, 2, 3,
and 4 in section 11.4.6.
When the DE bit in CHCR is cleared to 0, DMA transfer is suspended on the
corresponding channel. (During a DMA transfer in a DMABRG request, do not clear the
DE bit to 0 by accessing from the CPU.) The TE bit is not set in this case. Transfer ending
in this case follows the procedures described in 1, 2, 3, and 4 in section 11.4.6.
If the AE bit in DMAOR is set to 1 due to an address error, DMA transfer is suspended on
all channels in accordance with the procedures in 1, 2, 3, and 4 in section 11.4.6, and the
bus is passed to the CPU. Therefore, when the AE bit is set to 1, SAR, DAR, and
DMATCR values indicate the addresses for the DMA transfer to be performed next and the
remaining number of transfers. The TE bit is not set to 1 in this case. To resume DMA
transfer, first correct the channel settings that caused the address error. Next re-specify
DMARSRA/DMARSRB even if there is no change in resource. After that read AE = 1 and
then write AE = 0. Acceptance of external requests is suspended while the AE bit is set to
1, so a DMA transfer request must be reissued when resuming transfer. Acceptance of on-
chip peripheral module requests is also suspended, so when resuming transfer, the DMA
transfer request enable bit for the relevant on-chip peripheral module must be cleared to 0
before the new setting is made. DMABRG must be reset for DMABRG requests. See
section 11.6.2, DMABRG Reset for the procedure.