HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 511

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

• External request acceptance conditions
• Usage Notes
(3) On-Chip Peripheral Module Request Mode
In this mode, the DMAC performs a transfer in response to a transfer request signal (interrupt
request signal) from an on-chip peripheral module.
To output a transfer request from an on-chip peripheral module, set the DMA transfer request
enable bit for that module.
1.
2.
3.
4.
5.
The DMAC detects an external request (DREQ) at a low level or falling edge. Ensure to hold
the external request (DREQ) signal high when there is no DMA transfer request from an
external device after a power-on reset or manual reset.
When DMA transfer is resumed, check whether a DMA transfer request is being held.
When at least either of DMAOR.DME and CHCR.DE is 0, and DMAOR.NMIF,
DMAOR.AE, and CHCR.TE are all 0, the DMAC will hold an input external request
(DREQ: edge detection) until DMA transfer is either executed or canceled. Since DMA
transfer is not enabled in this case (DME = 0 or DE = 0), DMA transfer is not initiated.
DMA transfer is started after it is enabled (DME = 1, DE = 1, NMIF = 0, AE = 0, TE = 0).
If an external request (DREQ) is input while DMA transfer is enabled (DME = 1, DE = 1,
NMIF = 0, AE = 0, TE = 0), DMA transfer is started.
An external request (DREQ) will be ignored if it is input with TE = 1, NMIF = 1, or AE =
1 during a power-on reset or manual reset, in deep sleep mode or standby mode, or while
the DMAC is in the module standby state. Write 1 to CHCRn or CHSET or re-specify the
channel resource in DMARSRA or DMARSRB before enabling DMAC transfer in order
to resume DMA transfer in DMABRG mode.
A previously input external request will be canceled by the occurrence of an NMI
interrupt (NMIF = 1) or address error (AE = 1), or by a power-on reset or manual reset.
In this LSI, it is possible to cancel a previously input external request (DREQ). In external
request 2-channel mode, drive the DREQ pin high after clearing the DS bit in CHCRn to
0. In DMABRG mode, set the CHSET bit in CHCRn to 1.
Rev. 2.00 Feb. 12, 2010 Page 427 of 1330
REJ09B0554-0200