HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1091

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Notes: 1. The external device can write to this bit via the MFI. The on-chip CPU cannot write to
Bit
4
3
2, 1
0
2. If the on-chip CPU and the external device via the MFI access MFRAM concurrently,
3. Do not set the WT and RD bits simultaneously to 1.
4. Performs continuous writing to MFRAM in 32-bit units. Data with a length of less than 32
this bit.
the access via the MFI is handled first.
bits is not written to MFRAM.
Bit
Name
⎯
RD*
⎯
AI/AD
3
Initial
Value
0
0
All 0
0
R/W
R
R/W*
R
R/W*
1
1
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Read
Setting this bit to 1 reads the MFRAM data indicated by
MFIADR into MFIDATA.*
•
•
Reserved
These bits are always read as 0. The write value should
always be 0.
Address auto-increment/decrement
This bit is valid only when the LOCK bit is 1. Each time
an MFRAM read or write operation occurs, the value in
MFIADR is automatically changed by +4 or by -4.
0: Auto-increment (+4)
1: Auto-decrement (-4)
Setting the RD and LOCK bits simultaneously to 1
results in the continuous read mode, and enables
high-speed data transfer. The RD bit remains 1 until
the RD bit is next written to 0, or until the LOCK bit is
cleared to 0.
If not setting the LOCK bit simultaneously to 1,
reading of MFRAM is performed only once. The RD
bit is automatically cleared to 0
Rev. 2.00 Feb. 12, 2010 Page 1007 of 1330
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REJ09B0554-0200