HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 418

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
(8) Pipelined Access
When the RASD bit in MCR is set to 1, pipelined access is performed for faster access to
synchronous DRAM between an access by the CPU and an access by the DMAC or for
consecutive accesses by the DMAC. Since synchronous DRAM is internally divided into two or
four banks, after a READ or WRIT command is issued for one bank it is possible to issue a PRE,
ACTV, or other command during the CAS latency cycle, data latch cycle, or data write cycle for
shortening the access cycle.
When a read access is followed by another read access to the same row address, after a READ
command has been issued, another READ command is issued before the end of the data latch
cycle so that read data is on the data bus continuously. When an access is made to another row
address and a different bank, the PRE command or ACTV command can be issued during the
CAS latency cycle or data latch cycle. If there are consecutive access requests for different row
Rev. 2.00 Feb. 12, 2010 Page 334 of 1330
REJ09B0554-0200
DACKn
(SA: IO → memory)
CKIO
Bank
Precharge-sel
Adress
CSn
RD/WR
RAS
CASS
DQMn
D31-D0
(Write)
BS
CKE
Figure 10.25 Burst Write Timing (Different Row Addresses)
Tpr
H/L
Tpc
Tr
Row
Row
Row
Trw
Tc1
c1
c1
H/L
Tc2
c2
Tc3
c3
Tc4
c4
Tc5
c5
c5
H/L
Tc6
c6
Tc7
c7
Tc8
c8
Trw1
Trw1