HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 816

SH4 7760, 17 X17 256BGA, LCDC, U

HD6417760BL200AV

Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417760BL200AV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
20 000
The word select pin in this mode does not act as a system word start signal as in non-compressed
mode, but instead is used to indicate that the receiver can receive another data burst, or the
transmitter can transmit another data burst.
Figures 20.18 and 20.19 show the compressed mode data transfer, with burst mode disabled, and
enabled, respectively.
(1) Slave Receiver
This mode allows the module to receive a serial bit stream from another device and store it in
memory.
The shift register clock can be supplied from an external device or from an internal clock.
The word select pin is used as an input flow control. Assuming that SWSP = 0 if SSI_WS is high
then the module will receive the bit stream in blocks of 32 bits, one data bit per clock. If SSI_WS
goes low then the module will complete the current 32-bit block and then stop any further
reception, until SSI_WS goes high again.
Rev. 2.00 Feb. 12, 2010 Page 732 of 1330
REJ09B0554-0200
Figure 20.19 Compressed Data Format, Master Transmitter, and Burst Mode Enabled
Figure 20.18 Compressed Data Format, Master Transmitter, Burst Mode Disabled
SSI_SDATA
SSI_SCK
SSI_WS
SSI_SDATA
SSI_SCK
SSI_WS
TRMD = 1, CPEN = 1, SCKD = 1, SWSD = 1, SWSP = 0, BREN = 1
TRMD = 1, CPEN = 1, SCKD = 1, SWSD = 1, SWSP = 0, BREN = 0
MSB
MSB
Data word 1
Data word 1
LSB
LSB
MSB
MSB
Data word 2
Data word 2
LSB
LSB
Null data
Null data
MSB
MSB
Data word 3
Data word 3
LSB
LSB

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