HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 700

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 17.16 shows a sample SCIF initialization flowchart.
Rev. 2.00 Feb. 12, 2010 Page 616 of 1330
REJ09B0554-0200
in SCSCR (leaving TE, RE, TIE,
Set RTRG1-0 and TTRG1-0 bits
Set TE and RE bits in SCSCR
in SCFCR, and clear TFRST
Set TFRST and RFRST bits
Set external pins to be used
Set CKE1 and CKE0 bits
and RIE bits cleared to 0)
and ER flags in SCFSR,
(SCIF_CLK, SCIF_TXD,
Set data transfer format
After reading BRK, DR,
in SCFCR to 1 to clear
to 1, and set TIE, RIE,
1-bit interval elapsed?
Clear TE and RE bits
write 0 to clear them
Set value in SCBRR
and RFRST bits to 0
Start of initialization
End of initialization
and SCIF_RXD)
the FIFO buffer
in SCSCR to 0
and REIE bits
Figure 17.16 Sample SCIF Initialization Flowchart
in SCSMR
Yes
Wait
No
[1]
[2]
[3]
[4]
[5]
[6]
[1]
[2]
[3]
[4]
[5]
[6]
Leave the TE and RE bits cleared
to 0 until the initialization almost
ends. Be sure to clear the TIE,
RIE, TE, and RE bits to 0.
Set the CKE1 and CKE0 bits.
Set the data transfer format in
SCSMR.
Write a value corresponding to
the bit rate into SCBRR. This
is not necessary if an external
clock is used. Wait at least one
bit interval after this write before
moving to the next step.
Set the external pins to be used.
Set SCIF_RXD input for reception and
SCIF_TXD output for transmission.
The input/output of the SCIF_CLK pin
must match the setting of the
CKE1 and CKE0 bits.
Set the TE or RE bit in SCSCR
to 1. Also set the TIE, RIE, and
REIE bits to enable the SCIF_TXD,
SCIF_RXD, and SCIF_CLK pins to
be used. When transmitting, the
SCIF_TXD pin will go to the mark
state. When receiving in clocked
synchronous mode with the
synchronization clock output (clock
master) selected, a clock starts to
be output from the SCIF_CLK pin
at this point.