HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 507

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

11.3.20 DMA USB Control Register (DMAUCR)
DMAUCR is a 32-bit readable/writable register that specifies the start of USB DMA transfer
between the shared memory and synchronous DRAM, and the data alignment mode. The setting of
the data alignment mode is also valid for accesses to the USB from the CPU. For details of the
data alignment mode, see section 11.6.13, USB Endian Conversion Function.
Initial value:
Initial value:
Bit
31 to 18 ⎯
17
16
15 to 2
1
0
R/W:
R/W:
Bit:
Bit:
Bit Name
CVRT1
CVRT0
⎯
START
⎯
31
15
0
R
0
R
-
-
30
14
0
R
0
R
-
-
29
13
0
R
0
R
-
-
Initial Value
All 0
0
0
All 0
0
0
28
12
0
0
R
R
-
-
27
11
0
R
0
R
-
-
26
10
R
R
-
0
-
0
R/W
R
R/W
R/W
R
R/W
R
25
R
R
0
0
-
9
-
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Alignment Mode
00: Alignment is not performed
01: Byte boundary mode
10: Longword/word boundary mode
11: Setting prohibited
Reserved
These bits are always read as 0. The write value
should always be 0.
DMA Transfer Start
Setting this bit to 1 starts a USB DMA transfer.
When the USB DMA transfer is completed, this bit
is automatically cleared to 0.
•
0: Invalid
1: Starts a USB DMA transfer
•
0: USB DMA transfer is stopped
1: USB DMA transfer is being performed
Reserved
This bit is always read as 0. The write value
should always be 0.
24
R
R
0
0
8
-
-
When writing
When reading
23
R
R
0
0
7
-
-
Rev. 2.00 Feb. 12, 2010 Page 423 of 1330
22
R
R
0
0
6
-
-
21
R
R
0
5
0
-
-
20
R
R
0
0
4
-
-
19
R
R
0
3
0
-
-
REJ09B0554-0200
18
R
0
2
0
R
-
-
CVRT1CVRT0
START
R/W
R/W
17
0
1
0
R/W
16
0
0
R
0
-