HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 909

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

22.5.7
The CANTXPR registers are two 16-bit read/conditionally-write registers that contain any
transmit pending flags for the CAN module. CANTXPR1 controls Mailboxes 31 to 16, and
CANTXPR0 controls Mailboxes 15 to 1. The host CPU may set the CANTXPR bits to affect any
message being considered for transmission by writing a 1 to the corresponding bit location.
Writing a 0 has no effect. CANTXPR cannot be cleared by writing a 0, but it must be cleared by
setting the corresponding CANTXCR bits. CANTXPR may be read by the host CPU to determine
which, if any, transmissions are pending. There is a transmit pending bit for all Mailboxes except
for the Mailbox 0. Writing a 1 to a bit location when the mailbox is configured to receive will
have no effect, and will be automatically cleared when an internal arbitration for transmission
runs.
The HCAN2 will clear a transmit pending flag after successful transmission of its corresponding
or when a transmission abort is normally requested from TXCR. The CANTXPR flag is not
cleared if the message is not transmitted due to the CAN node losing the arbitration process or due
to errors on the CAN bus, and HCAN2 automatically tries to transmit it again until its DART
(Disable Automatic Re-Transmission) bit is set in the Message-Control of the corresponding
Mailbox. In such case (DART is set), the transmission is cleared and notified through Mailbox
Empty Interrupt Flag (IRR8) and the correspondent bit in the Abort Acknowledgement Register
(CANABACK).
If the status of CANTXPR changes, the HCAN2 shall ensure that in the identifier priority scheme
(MCR2 = 0), the highest priority message is always presented for transmission in an intelligent
way even under circumstances such as bus arbitration losses or errors on the CAN bus. Please
refer to section 22.6 Operation in details.
When the HCAN2 changes state of nay CANTXPR bit position to 0, an empty slot interrupt
(IRR8) may be generated. This indicates that either successful or an aborted mailbox transmission
has been made. If a message transmission is successful it is signaled in the CANTXACK, and if a
message transmission abortion is successful it is signaled in the CANABACK. By checking these
registers, the contents of the Message-Data of the corresponding Mailbox may be modified to
prepare for the next transmission.
• CANTXPR1
Initial value:
R/W:
Bit:
Transmit Pending Request Registers 1 and 0 (CANTXPR1, CANTXPR0)
TXPR1
R/W*
_15
15
0
TXPR1
R/W*
_14
14
0
TXPR1
R/W*
_13
13
0
TXPR1
R/W*
_12
12
0
TXPR1
R/W*
_11
11
0
TXPR1
R/W*
_10
10
0
TXPR1
R/W*
_9
9
0
TXPR1
R/W*
_8
8
0
TXPR1
R/W*
_7
0
7
TXPR1
Rev. 2.00 Feb. 12, 2010 Page 825 of 1330
R/W*
_6
6
0
TXPR1
R/W*
_5
5
0
TXPR1
R/W*
_4
4
0
TXPR1
R/W*
_3
3
0
REJ09B0554-0200
TXPR1
R/W*
_2
2
0
TXPR1
R/W*
_1
1
0
TXPR1
R/W*
_0
0
0