HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 478

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
17
16
15
14
Rev. 2.00 Feb. 12, 2010 Page 394 of 1330
REJ09B0554-0200
Bit Name
AM
AL
DM1
DM0
Initial Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
Acknowledge Mode
In dual address mode, selects whether DACK is
output in the data read cycle or write cycle.
In single address mode, DACK is always output
regardless of the setting of this bit.
In external request 2-channel mode, this bit is
valid only in CHCR0 and CHCR1.
In DMABRG mode, this bit is valid in CHCR0 to
CHCR7.
0: DACK is output in read cycles
1: DACK is output in write cycles
Acknowledge Level
Specifies the DACK signal as active-high or
active-low.
In external request 2-channel mode, this bit is
valid only in CHCR0 and CHCR1.
In DMABRG mode, this bit is invalid and the
DACK polarity is specified by bits AL3 to AL0 in
DMARCR.
0: Active-high output
1: Active-low output
Destination Address Mode 1 and 0
These bits specify incrementing/decrementing of
the DMA transfer destination address. The
specification of these bits is ignored when data is
transferred from external memory to an external
device in single address mode.
00: Destination address fixed
01: Destination address incremented (+1 in 8-bit
10: Destination address decremented (–1 in 8-bit
11: Setting prohibited
transfer, +2 in 16-bit transfer, +4 in 32-bit
transfer, +8 in 64-bit transfer, +32 in 32-byte
burst transfer)
transfer, –2 in 16-bit transfer, –4 in 32-bit
transfer, –8 in 64-bit transfer, –32 in 32-byte
burst transfer)