HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1212

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

31.2.6
BBRB is a 16-bit readable/writable register that specifies three conditions from among the channel
B break conditions: instruction access/operand access, read/write, and operand size.
Initial value:
Note: x: Don't care
Rev. 2.00 Feb. 12, 2010 Page 1128 of 1330
REJ09B0554-0200
Bit
15 to 7
5
4
3
2
6
1
0
R/W:
Bit:
Break Bus Cycle Register B (BBRB)
Bit Name Initial Value R/W
—
IDB1
IDB0
RWB1
RWB0
SZB2
SZB1
SZB0
15
R
0
-
14
-
R
0
All 0
0
0
0
0
0
0
0
13
R
0
-
12
R
0
-
11
R
0
-
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
10
R
0
-
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Instruction Access/Operand Access Select B
These bits specify whether an instruction access cycle
or an operand access cycle is used as the bus cycle
in the channel B break conditions.
00: Condition comparison is not performed
01: Instruction access cycle is used as break condition
10: Operand access cycle is used as break condition
11: Instruction access cycle or operand access cycle
Read/Write Select B
These bits specify whether a read cycle or write cycle
is used as the bus cycle in the channel B break
conditions.
00: Condition comparison is not performed
01: Read cycle is used as break condition
10: Write cycle is used as break condition
11: Read cycle or write cycle is used as break
Operand Size Select B
These bits select the operand size of the bus cycle
used as a channel B break conditions.
000: Operand size is not included in break conditions
001: Byte access is used as break condition
010: Word access is used as break condition
011: Longword access is used as break condition
100: Quadword access is used as break condition
101: Setting prohibited
11x: Setting prohibited
R
9
0
-
is used as break condition
condition
R
8
0
-
R
7
0
-
SZB2 IDB1
R/W
6
0
R/W
5
0
IDB0 RWB1 RWB0 SZB1
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
SZB0
R/W
0
0