HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 327

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

9.5
9.5.1
The sequence of operations when an interrupt is generated is described below. Figure 9.3 shows a
flowchart of the interrupt operations.
1. The interrupt request sources send interrupt request signals to the interrupt controller.
2. The interrupt controller selects the highest-priority interrupt from the interrupt requests sent,
3. The priority level of the interrupt selected by the interrupt controller is compared with the
4. The CPU accepts an interrupt between instructions.
5. The interrupt source code is set in the interrupt event register (INTEVT).
6. The contents of the status register (SR) and program counter (PC) are saved to SSR and SPC,
7. The block bit (BL), mode bit (MD), and register bank bit (RB) in SR are set to 1.
8. The CPU jumps to the start address of the interrupt-related exception handling routine (the sum
The exception handling routine may branch with the INTEVT value as its offset in order to
identify the interrupt source. This enables it to easily branch to the handling routine for the
particular interrupt source.
Notes: 1. In this LSI, the interrupt mask level bits (IMASK3 to IMASK0) in the status register
according to the priority levels set in IPRA to IPRD and INTPRI00 to INTPRI0C. Lower-
priority interrupts are held pending. If two of these interrupts have the same priority level, or if
multiple interrupts occur within a single module, the interrupt with the highest priority
according to table 9.4 is selected.
interrupt mask level (IMASK3 to IMASK0) in SR of the CPU. If the request's priority level is
higher than the level in bits IMASK3 to IMASK0, the interrupt controller accepts the interrupt
and sends an interrupt request signal to the CPU.
respectively. The R15 contents at this time are saved in SGR.
of the value set in the vector base register (VBR) and H'0000 0600).
2. Clear the interrupt source flag during the interrupt handling routine.
3. For some interrupt sources, the interrupt masks (INTMSK00 and INTMSK04) must be
Interrupt Operation Sequence
Operation
(SR) of the CPU are not changed by acceptance of an interrupt.
To ensure that the cleared interrupt source is not inadvertently accepted again, read the
interrupt source flag after it has been cleared, wait for the interval shown in table 9.8,
and then clear the BL bit or execute an RTE instruction.
cleared using INTMSKCLR00 and INTMSKCLR04.
Rev. 2.00 Feb. 12, 2010 Page 243 of 1330
REJ09B0554-0200