HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 503

SH4 7760, 17 X17 256BGA, LCDC, U

HD6417760BL200AV

Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417760BL200AV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
20 000
RAM1 RAM0 Size
0
0
1
TAM1 TAM0 Size
0
0
1
Table 11.5 (1)
Table 11.5 (2)
11.3.15 DMA Audio Transmit Transfer Counter (DMAATXTCNT)
DMAATXTCNT is a 32-bit read-only register that indicates the number of bytes remaining to be
transferred in the transfer bytes specified by DMAATXTCR. This register is write-prohibited.
DMAATXTCNT0 corresponds to HAC(0) or SSI(0) and DMAATXTCNT1 corresponds to
HAC(1) or SSI(1). Writing 1 to the TDE bit in DMAACR sets the DMAATXTCR value in this
register. On forced termination, the number of transfer bytes remaining at that time is indicated.
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
0
1
0
0
1
0
31
15
R
R
-
-
No Alignment
(One longword)
Longword (four bytes)
Longword (two words)
No Alignment
(One longword)
Longword (four bytes)
Longword (two words)
30
14
R
R
-
-
Data Alignment for Receive Slot Data and External Bus
Data Alignment for Transmit Slot Data and External Bus
29
13
R
R
-
-
28
12
R
R
-
-
27
11
R
R
-
-
26
10
R
R
-
-
31 to
24
D3
D0
D1
31 to
24
D3
D3
D3
25
R
R
9
-
-
23 to
16
D2
D1
D0
23 to
16
D2
D2
D2
Data Bus
Data Bus
24
R
R
8
-
-
15 to
8
D1
D2
D3
15 to
8
D1
D1
D1
23
R
R
7
-
-
Rev. 2.00 Feb. 12, 2010 Page 419 of 1330
22
R
R
6
-
-
7 to
0
D0
D3
D2
7 to
0
D0
D0
D0
21
R
R
5
-
-
31 to
24
D3
D3
31 to
24
D3
D1
D3
D0
20
R
R
4
-
-
23 to
16
D2
D2
D2
23 to
16
D2
D1
D0
19
R
R
3
-
-
Slot Data
Slot Data
REJ09B0554-0200
18
R
R
-
2
-
15 to
8
D1
D1
D1
15 to
8
D1
D2
D3
17
R
R
1
-
-
7 to
0
D0
D0
D0
7 to
0
D0
D3
D2
16
R
R
-
0
-

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