HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 580

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

12.4.2
DCKDR is a 32-bit readable/writable register that specifies use/non-use of clock output from the
DCK pin and the DCK clock frequency division ratio.
By setting the DIV1 and DIV0 bits, the CKIO clock is divided by 1, 2, or 3 and supplied to the
DCK pin. This division ratio setting also allows the DCK clock to be extended to become one to
three CKIO cycles even while BS2 is being asserted. For details on adjustment of the CS negate
time, see the description of WCR4.
Initial value:
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 496 of 1330
REJ09B0554-0200
Bit
31 to 8
7
6 to 4
3
2
R/W:
R/W:
Bit:
Bit:
Clock Division Register (DCKDR)
Bit Name
—
DCKEN
—
PLL3EN
DCKOUT
31
15
R
R
0
0
-
-
30
14
-
R
-
R
0
0
29
13
R
R
0
0
-
-
Initial Value
All 0
0
All 0
0
0
28
12
R
R
0
0
-
-
27
11
R
R
0
0
-
-
26
10
R
R
-
0
-
0
R/W
R
R
R
R/W
R/W
25
R
R
-
0
9
-
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
(usable).
0: Unstable (unusable)
1: Stable (usable)
Reserved
These bits are always read as 0. The write value
should always be 0.
PLL Circuit 3 Enable
Specifies whether PLL circuit 3 is on or off.
Writing 1 to this bit turns the on-chip PLL circuit 3
on.
0: PLL circuit 3 is not used. In this case, the DCK
1: PLL circuit 3 is used.
DCK Output Control
Controls the DCK pin state. Writing 1 to this bit
sets the DCK pin at the output state.
0: DCK pin goes to high-impedance state
1: Clock is output from DCK pin
Indicates whether the DCK output clock is stable
24
R
R
0
8
0
-
-
output is fixed at 1.
DCK
EN
23
R
R
0
7
0
-
22
R
R
0
6
0
-
-
21
R
R
0
5
0
-
-
20
R
R
0
4
0
-
-
PLL3
R/W
EN
19
R
0
3
0
-
DCK
OUT
R/W
18
R
0
2
0
-
DIV1
R/W
17
R
0
1
0
-
DIV0
R/W
16
R
0
0
1
-