HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 547

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

(3) Notes on Transfer End
When DMA transfer ends, requests may be retained in DMAC. Following are examples of
cancellation of requests retained in DMAC.
• External requests
• On-chip peripheral module requests
2. End of transfer with DMAOR.NMIF = 1
3. End of transfer with DMAOR.DME = 0
See item 5 in External Request Acceptance Conditions in section 11.4.2, DMA Transfer
Requests (2) External Request Mode.
Retained requests may be processed if DMA transfer occurs. If DMARCR.REXn = 1 when
DMA transfer ends then external requests will be retained in DMAC. Examples of processing
are shown below.
1. After DMA transfer ends, set the corresponding resources in DMARSRA or DMARSRB to
2. Read Bit REXn corresponding to the channel in DMARCR.
If the NMIF bit in DMAOR is set to 1 due to an NMI interrupt, DMA transfer is suspended
on all channels in accordance with the procedures in 1, 2, 3, and 4 in section 11.4.6, and the
bus is passed to the CPU. Therefore, when NMIF is set to 1, the SAR, DAR, and
DMATCR values indicate the addresses for the DMA transfer to be performed next and the
remaining number of transfers. The TE bit is not set to 1 in this case. To resume DMA
transfer after NMI interrupt handling is completed, first re-specify
DMARSRA/DMARSRB even when there is no resource change. After that read NMIF = 1
and then write NMIF = 0. Acceptance of external requests is suspended while the NMIF bit
is set to 1, so a DMA transfer request must be reissued when resuming transfer. Acceptance
of on-chip peripheral module requests is also suspended, so when resuming transfer, the
DMA transfer request enable bit for the relevant on-chip peripheral module must be cleared
to 0 before the new setting is made. DMABRG must be reset for DMABRG requests. See
section 11.6.2, DMABRG Reset for the procedure.
If the DME bit in DMAOR is cleared to 0, DMA transfer is suspended on all channels in
accordance with the procedures in 1, 2, 3, and 4 in section 11.4.6, and the bus is passed to
the CPU. The TE bit is not set to 1 in this case. When the DME bit is cleared to 0, the SAR,
DAR, and DMATCR values indicate the addresses for the DMA transfer to be performed
next and the remaining number of transfers. When resuming transfer, set DME to 1.
Operation will then be resumed from the next transfer.
H'00. (Write H'80.)
REXn = 0: The DMAC has not accepted (retained) a transfer request. Go to 9.
REXn = 1: The DMAC has accepted (retained) a transfer request. Go to 3.
Rev. 2.00 Feb. 12, 2010 Page 463 of 1330
REJ09B0554-0200