HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1033

SH4 7760, 17 X17 256BGA, LCDC, U

HD6417760BL200AV

Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417760BL200AV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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HD6417760BL200AV
Manufacturer:
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26.3.7
CMDSTRT is an 8-bit readable/writable register that triggers the start of command transmission,
representing the start of a command sequence. The following operations should have been
completed before the command sequence starts.
• Analysis of prior command response, clearing the command response register write if
• Analysis/transfer of receive data of prior command if necessary
• Preparation of transmit data of the next command if necessary
• Setting of CMDTYR, RSPTYR, and TBCR
• Setting of CMDR0 to CMDR4
Command sequences are controlled by the sequencers in both the MMCIF side and the MMC card
side. Normally, these operate synchronously. However, if an error occurs or a command is
aborted, these may become temporarily unsynchronized. Be careful when setting the CMDOFF bit
in OPCR, issuing the CMD12 command, or processing an error in MMC mode. A new command
sequence should be started only after the end of the command sequence on both the MMCIF and
card sides is confirmed.
Bit
7 to 0
Bit
7 to 1
0
necessary
The CMDR0 to CMDR4, CMDTYR, RSPTYR, and TBCR registers should not be changed
until command transmission has ended (the CWRE flag in CSTR has been set to 1).
Command Start Register (CMDSTRT)
Bit
Name
RSPR
Bit
Name
START
Initial
Value
All 0
Initial
Value
All 0
0
Initial value:
R/W:
Bit:
R/W
R/W
R/W
R
R/W
7
-
0
R
Description
These bits are cleared to H'00 by writing an arbitrary value.
RSPR0 to RSPR16 comprise a continuous 17-byte shift
register.
R
6
0
-
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Starts command transmission when 1 is written. This bit is
automatically cleared. When 0 is written to this bit, its
previous value is retained.
R
5
0
-
4
0
R
-
R
3
0
-
Rev. 2.00 Feb. 12, 2010 Page 949 of 1330
2
0
R
-
R
1
0
-
START
R/W
0
0
REJ09B0554-0200

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