HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 358

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

10.5.6
WCR2 is a 32-bit readable/writable register that specifies the number of wait cycles to be inserted
for each area. It also specifies the data access pitch when performing burst ROM memory access.
Initial value:
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 274 of 1330
REJ09B0554-0200
Bit
31
30
29
R/W:
R/W:
Bit:
Bit:
Bit
Name
A6W2
A6W1
A6W0
Wait Control Register 2 (WCR2)
A6W2 A6W1 A6W0
A3W2 A3W1 A3W0
R/W
R/W
31
15
1
1
R/W
R/W
30
14
1
1
Initial
Value
1
1
1
R/W
R/W
29
13
1
1
A6B2 A6B1 A6B0
R/W
28
12
R
1
0
-
R/W
R/W
R/W
R/W
A2W2 A2W1 A2W0 A1W2 A1W1 A1W0 A0W2 A0W1 A0W0
R/W
R/W
27
11
1
1
R/W
R/W
26
10
1
1
Description
Area 6 Wait Control
These bits specify the number of wait cycles to be
inserted for area 6. For the case where an MPX interface
setting is made, see table 10.7.
000:
001:
010:
011:
100:
101:
110:
111:
A5W2 A5W1 A5W0 A5B2 A5B1 A5B0 A4W2 A4W1 A4W0
R/W
R/W
25
1
9
1
R/W
R/W
24
Inserted wait cycles
0
1
2
3
6
9
12
15
1
8
1
R/W
R/W
23
1
7
1
R/W
R/W
22
1
6
1
R/W
R/W
21
1
5
1
R/W
R/W
20
1
4
1
R/W
R/W
RDY pin
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
19
1
3
1
A0B2 A0B1 A0B0
R/W
R/W
18
1
2
1
R/W
R/W
17
1
1
1
R/W
16
R
0
0
1
-