HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1133

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

29.4.2
In multi mode, analog inputs for the specified channels (one or more) are converted once each as
shown below.
1. When the ADST bit in ADCSR is set to 1 by software, A/D conversion starts with the first
2. When multiple channels are selected, the input signal for the second channel is converted after
3. When conversion of each channel ends, the conversion results are transmitted to the A/D
4. When conversion of all selected channel ends, the ADF bit of ADCSR is set to 1. If the ADIE
5. When A/D conversion ends, the ADST bit is automatically cleared to 0 and the A/D converter
Typical operations when three channels (AN0 to AN2) are selected in multi mode are described
below. Figure 29.3 shows a timing diagram for this example.
1. Select multi mode as the operating mode (MDS1 = 1 and MDS0 = 0) and AN0 to AN2 as the
2. A/D conversion of the first channel (AN0) starts. When the conversion ends, the result is
3. Conversion proceeds in the same way up to the third channel (AN2).
4. When conversion of all selected channels (AN0 to AN2) ends, the ADF bit is set to 1 and the
channel (AN0).
the A/D conversion for the first channel ends.
conversion data register that corresponds to the channel.
bit is also set to 1, an ADI interrupt is requested at this time.
becomes idle. When the ADST bit is cleared to 0 during A/D conversion, the conversion is
halted and the A/D converter becomes idle.
Writing 0 to the ADF bit after reading ADF = 1 clears the ADF bit.
analog input channels (CH1 = 1 and CH0 = 0). Then start A/D conversion (ADST = 1).
transferred into ADDRA. Next, the second channel (AN1) is selected automatically and A/D
conversion starts.
ADST bit is cleared to 0 to stop A/D conversion.
If the DMASL bit is cleared to 0 and the ADIE bit is set to 1 at this time, an ADI interrupt is
generated after A/D conversion ends.
Multi Mode
Rev. 2.00 Feb. 12, 2010 Page 1049 of 1330
REJ09B0554-0200