HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 805

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

20.3.3
SSITDR is a 32-bit register that stores data to be transmitted.
Data written to SSITDR is transferred to the shift register as it is required for transmission. If the
data word length is less than 32 bits then its alignment should be as defined by the PDTA control
bit.
Reading this register will return the data in the buffer.
Initial value:
Initial value:
20.3.4
SSIRDR is a 32-bit register that stores the received data.
Data in SSIRDR is transferred from the shift register as each data word is received. If the data
word length is less than 32 bits then its alignment should be as defined by the PDTA control bit in
SSICR.
Initial value:
Initial value:
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
Receive Data Register (SSIRDR)
Transmit Data Register (SSITDR)
R/W
R/W
31
15
31
15
R
R
0
0
0
0
R/W
R/W
30
14
30
14
0
0
0
0
R
R
R/W
R/W
29
13
29
13
R
R
0
0
0
0
R/W
R/W
28
12
28
12
R
R
0
0
0
0
R/W
R/W
27
11
27
11
R
R
0
0
0
0
R/W
R/W
26
10
26
10
0
0
0
0
R
R
R/W
R/W
25
25
0
0
0
0
R
R
9
9
R/W
R/W
24
24
0
8
0
0
R
8
0
R
R/W
R/W
23
23
R
R
0
7
0
0
7
0
Rev. 2.00 Feb. 12, 2010 Page 721 of 1330
R/W
R/W
22
22
R
R
0
6
0
0
6
0
R/W
R/W
21
21
R
R
0
5
0
0
5
0
R/W
R/W
20
20
R
R
4
4
0
0
0
0
R/W
R/W
19
19
3
3
0
0
0
R
0
R
REJ09B0554-0200
R/W
R/W
18
18
2
R
2
R
0
0
0
0
R/W
R/W
17
17
R
R
1
1
0
0
0
0
R/W
R/W
16
16
0
0
0
0
0
0
R
R