HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 697

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Note: * Reception continues even when a parity error or framing error occurs.
4. If the RIE bit in SCSCR is set to 1 when the RDF or DR flag changes to 1, a receive-FIFO-
Figure 17.13 shows an example of the operation for reception in asynchronous mode.
5. When modem control is enabled, the SCIF_RTS signal is output when SCFRDR is empty.
C. Overrun error check: The SCIF checks that the ORER flag is 0, indicating that no overrun
D. Break check: The SCIF checks that the BRK flag is 0, indicating that the break state is not
data-full interrupt (RXI) request is generated.
If the RIE bit or REIE bit in SCSCR is set to 1 when the ER flag changes to 1, a receive-error
interrupt (ERI) request is generated.
If the RIE bit or REIE bit in SCSCR is set to 1 when the BRK or ORER flag changes to 1, a
break reception interrupt (BRI) request is generated.
When SCIF_RTS is 0, reception is possible. When SCIF_RTS is 1, this indicates that
SCFRDR contains bytes of data equal to or more than the SCIF_RTS output active trigger
number.The SCIF_RTS output active trigger value is specified by bits 10 to 8 in the FIFO
control register (SCFCR). For details, see section 17.3.9, FIFO control register (SCFCR). In
addition, SCIF_RTS is also 1 when the RE bit in SCSCR is cleared to 0.
Figure 17.14 shows an example of the operation when modem control is used.
error has occurred.*
set.*
If (b), (c), and (d) checks are passed, the receive data is stored in SCFRDR.
Serial
data
RDF
FER
1
Start
bit
0
D0
(Example with 8-Bit Data, Parity, One Stop Bit)
Figure 17.13 Sample SCIF Receive Operation
One frame
D1
Data
D7
RXI interrupt
request
Parity
bit
0/1
Stop
bit
1
Start
bit
0/1
Data read and RDF flag
read as 1 then cleared to
0 by RXI interrupt handler
D0
D1
Rev. 2.00 Feb. 12, 2010 Page 613 of 1330
Data
D7
Parity
bit
0/1
Stop
bit
ERI interrupt request
generated by receive
error
0
REJ09B0554-0200
0/1