HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 781

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

19.4.10 Standby Mode
Communications are unavailable in standby mode because clock supply stops. When entering the
standby mode, terminate communications and check the status of the registers using the steps
described below.
Carry out the following steps if communications are in progress:
1. When completing communication in I
2. When completing communication in I
Carry out the following steps if communications are NOT in progress:
1. Check that the MIE bit of ICMCR is 0.
2. Check that the SIE bit of ICSCR is 0.
3. Monitor the status of the FSCL and FSDA bits of ICMCR to check that FSCL is 1 and FSDA
19.5
In FIFO mode, the 16-stage FIFO buffer can be used. Registers related to the FIFO mode are
ICFCR, ICFSR, ICFIER, ICRFDR, and ICTFDR. For details, refer to the description of these
registers.
In FIFO mode, interrupt overhead can be reduced since transfer is performed in units of bytes
specified by ICFCR.
19.5.1
1. The MDE bit and the MAT bit are set to 1 at the same timing, as in single buffer mode. At this
2. FSB must be set to 1 at least one SCL clock cycle after the transmit FIFO data empty flag
and clear the MIE bit of ICMCR to 0.
clear SIE bit of ICSCR to 0.
is 0. (Determine the timing for monitoring according to the SCL frequency to be used). When
the MIE and SIE bits are 1, check that communications are not in progress and clear these bits
to 0.
time, the ESG bit should be cleared to 0. The master device holds SCL low level until the
MDE bit is cleared to 0 in order to suspend data transfer.
(TDFE) is set, and within 9 SCL clock cycles following that flag being set. (See figure
19.15.)* For example, to transfer 3 bytes of data, after 3 bytes of data have been written to the
FIFO and transferred, verify that TDFE = 1 either by poling or with the transmit FIFO data
empty (TXI) interrupt and then set FSB after the first SCL clock cycle and before the ninth
SCL clock cycle completes following TDFE being set to 1. Note that care is required
Master Transmitter Operation (FIFO Buffer Mode)
FIFO Mode Operation
2
2
C master mode, check that the MST bit of ICMSR is 1
C slave mode, check that SSR bit of ICSSR is 1 and
Rev. 2.00 Feb. 12, 2010 Page 697 of 1330
Section 19 I
REJ09B0554-0200
2
C Bus Interface