HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 67

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 16 Compare Match Timer (CMT)
Figure 16.1 Block Diagram of CMT .........................................................................................547
Figure 16.2 Edge Detection .......................................................................................................560
Figure 16.3 32-Bit Timer Mode: Input Capture.........................................................................560
Figure 16.4 Output Pin Assertion Period...................................................................................561
Figure 16.5 32-Bit Timer Mode: Output Compare....................................................................561
Figure 16.6 16-Bit Timer Mode: Input Capture.........................................................................562
Figure 16.7 16-Bit Timer Mode: Output Compare....................................................................563
Figure 16.8 Updown-Counter Mode..........................................................................................564
Figure 16.9 Up-Counter Mode...................................................................................................564
Figure 16.10 Up-Counter with Capture Mode.............................................................................565
Figure 16.11 Rotary Mode...........................................................................................................566
Section 17 Serial Communication Interface with FIFO (SCIF)
Figure 17.1 Block Diagram of SCIF..........................................................................................569
Figure 17.2 SCIF_RTS Pin (Only in Channels 1 and 2)............................................................570
Figure 17.3 SCIF_CTS Pin (Only in Channels 1 and 2)............................................................570
Figure 17.4 SCIF_CLK Pin ....................................................................................................... 571
Figure 17.5 SCIF_TXD Pin .......................................................................................................572
Figure 17.6 SCIF_RXD Pin....................................................................................................... 572
Figure 17.7 Data Format in Asynchronous Communication
Figure 17.8 Sample SCIF Initialization Flowchart ....................................................................607
Figure 17.9 Sample Serial Transmission Flowchart ..................................................................608
Figure 17.10 Sample SCIF Transmission Operation
Figure 17.11 Sample Operation Using Modem Control (SCIF_CTS)
Figure 17.12 Sample Serial Reception Flowchart (1)..................................................................611
Figure 17.12 Sample Serial Reception Flowchart (2)..................................................................612
Figure 17.13 Sample SCIF Receive Operation (Example with 8-Bit Data, Parity,
Figure 17.14 Sample Operation Using Modem Control (SCIF_RTS)
Figure 17.15 Data Format in Synchronous Communication .......................................................614
Figure 17.16 Sample SCIF Initialization Flowchart ....................................................................616
Figure 17.17 Sample Serial Transmission Flowchart ..................................................................617
Figure 17.18 Sample SCIF Transmission Operation in Synchronous Mode ...............................618
Figure 17.19 Sample Serial Reception Flowchart (1)..................................................................619
Figure 17.19 Sample Serial Reception Flowchart (2)..................................................................620
Figure 17.20 Sample SCIF Reception Operation in Synchronous Mode ....................................620
Figure 17.21 Sample Simultaneous Serial Transmission and Reception Flowchart....................621
(Example with 8-Bit Data, Parity, and Two Stop Bits) ..........................................604
(Example with 8-Bit Data, Parity, One Stop Bit) ...................................................609
(Only in Channels 1 and 2).....................................................................................610
One Stop Bit)..........................................................................................................613
(Only in Channels 1 and 2).....................................................................................614
Rev. 2.00 Feb. 12, 2010 Page lxv of lxxxii
REJ09B0554-0200