HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 310

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table 9.3
Register
IPRA
IPRB
IPRC
IPRD
Notes: 1. REF is the memory refresh control unit in the bus state controller (BSC). See section
As shown in table 9.3, four peripheral modules are assigned to each register. Setting a value from
H'F (1111) to H'0 (0000) in each of the 4-bit groups, 15 to 12, 11 to 8, 7 to 4, and 3 to 0,
configures interrupt priority level for each group. Setting H'F designates priority level 15 (the
highest level), and setting H'0 designates priority level 0 (requests are masked).
9.3.2
INTPRI00 to INTPRI0C are 32-bit readable/writable registers that set priority levels from 15 to 0
for the peripheral module interrupts.
Initial value:
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 226 of 1330
REJ09B0554-0200
Bit
31 to 0
R/W:
R/W:
Bit:
Bit:
2. Reserved: These bits are always read as 0. The write value should always be 0.
3. These bits set the interrupt priority level of the GPIO in normal mode and that of the
Interrupt Priority Level Setting Registers 00 to 0C (INTPRI00 to INTPRI0C)
Bit Name
R/W
R/W
10, Bus State Controller (BSC), for details.
GPIO, IRL, IRQ4, and IRQ5 in software standby mode. To exit software standby mode
by an IRQ4 or IRQ5 interrupt, INTPRI00 must also be set. The same value must be set
in both registers. Note that software standby mode cannot be exited by an IRQ6 or
IRQ7 interrupt.
31
15
0
0
Interrupt Request Sources and IPRA to IPRD
R/W
R/W
30
14
0
0
15 to 12
TMU0
WDT
GPIO (IRL, IRQ)*
IRL0
R/W
R/W
29
13
0
0
Initial Value
All 0
R/W
R/W
28
12
0
0
R/W
R/W
27
11
0
0
3
R/W
R/W
26
10
0
0
R/W
R/W
11 to 8
TMU1
REF*
DMAC
IRL1
R/W
R/W
25
0
9
0
1
Description
These bits set the priority level for each interrupt
source in 4-bit units. For details, see table 9.4,
Interrupt Request Sources and INTPRI00 to
INTPRI0C.
R/W
R/W
24
0
8
0
R/W
R/W
23
Bits
0
7
0
7 to 4
TMU2
Reserved*
Reserved*
IRL2
R/W
R/W
22
0
0
6
R/W
R/W
21
0
5
0
2
2
R/W
R/W
20
0
4
0
R/W
R/W
19
3 to 0
Reserved*
Reserved*
H-UDI
IRL3
0
3
0
R/W
R/W
18
0
2
0
R/W
R/W
2
2
17
0
1
0
R/W
R/W
16
0
0
0