HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1067

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

• The end of the command sequence is detected by poling the BUSY flag in CSTR, data transfer
• The data busy state is checked through DTBUSY in CSTR. If the card is in data busy state, the
Note: In a write to the card by stream transfer, the MMCIF continues data transfer to the card
(FIFO_EMPTY)
(DTBUSY_TU)
Input/output pins
end interrupt (DTI), or data response interrupt (DRPI).
end of the data busy state is detected by the data busy end interrupt (DBSYI).
CMDSTRT
(DTBUSY)
INTSTR0
MCCMD
(DATAEN)
MCCLK
(START)
(DBSYI)
(CWRE)
MCDAT
(BUSY)
(CMDI)
(CRPI)
(REQ)
(DRPI)
OPCR
CSTR
(FEI)
(DTI)
Figure 26.15 Example of Command Sequence for Commands with Write Data
even after a FIFO empty interrupt is detected. In this case, complete the command
sequence after at least 24 transfer clock cycles.
CMD24(WRITE_SINGLE_BLOCK)
Command
transmission
started
Command
Single block write command execution sequence
(Block Size ≤ FIFO Size)
Command
response
Write data
Rev. 2.00 Feb. 12, 2010 Page 983 of 1330
Status
Busy
REJ09B0554-0200