HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 698

SH4 7760, 17 X17 256BGA, LCDC, U

HD6417760BL200AV

Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417760BL200AV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
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17.4.3
Synchronous mode, in which data is transmitted or received in synchronization with clock pulses,
is suitable for fast serial communication.
Since the transmitter and receiver are independent units in the SCIF, full-duplex communication
can be achieved by sharing the clock. Both the transmitter and receiver have a 128-stage FIFO
buffer structure, so that data can be read or written during transmission or reception, enabling
continuous data transfer and reception.
Figure 17.15 shows the general format for synchronous communication.
In synchronous serial communication, data on the communication line is output from one fall of
the synchronization clock to the next fall. Data is guaranteed to be accurate at the start of the
synchronization clock.
In serial communication, each character is output starting with the LSB and ending with the MSB.
After the MSB is output, the communication line remains in the state of the last data.
In synchronous mode, the SCIF receives data in synchronization with the rise of the
synchronization clock.
Rev. 2.00 Feb. 12, 2010 Page 614 of 1330
REJ09B0554-0200
SCIF_RXD
SCIF_RTS
Serial data
Operation in Synchronous Mode
Synchronization
clock
Serial data
Note: * High except in continuous transfer
Figure 17.14 Sample Operation Using Modem Control (SCIF_RTS)
Figure 17.15 Data Format in Synchronous Communication
Start
bit
0
Don’t care
D0
*
D1 D2
LSB
Bit 0
(Only in Channels 1 and 2)
Bit 1
D7 0/1 1
One unit of transfer data (character or frame)
Parity
bit
Bit 2
Stop
bit
Bit 3
Bit 4
Bit 5
Start
bit
0
Bit 6
Bit 7
MSB
Don’t care
*

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