HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 86

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

The features of this LSI are listed in table 1.1.
Table 1.1
Item
LSI
CPU
Rev. 2.00 Feb. 12, 2010 Page 2 of 1330
REJ09B0554-0200
Features
Features
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Operating frequency: 200 MHz
Performance: 360MIPS, 1.4 GFLOPS
Voltage: 1.5 V (internal), 3.3 V (I/O)
Superscalar architecture: Parallel execution of two instructions
Packages: 256-pin BGA (Size: 17 × 17 mm, pin pitch: 0.8 mm)
External buses:
⎯ Separate 26-bit address and 32-bit data buses
⎯ External bus frequency: 67MHz
Choice of MFI mode or LCD mode:
⎯ MFI mode: 8-/16-bit parallel interface
⎯ LCD mode: LCD controller/data output
Original Renesas Technology SuperH architecture
32-bit internal data bus
General register file:
⎯ Sixteen 32-bit general registers (and eight 32-bit shadow registers)
⎯ Seven 32-bit control registers
⎯ Four 32-bit system registers
RISC-type instruction set (upward-compatible with SH-1, SH-2, and SH-3)
⎯ Fixed 16-bit instruction length for improved code efficiency
⎯ Load-store architecture
⎯ Delayed branch instructions
⎯ Conditional execution
⎯ C-based instruction set
Superscalar architecture (providing simultaneous execution of two
instructions) including FPU
Instruction execution time: Maximum 2 instructions/cycle
Virtual address space: 4 Gbytes (448-Mbyte external memory space)
Space identifier ASIDs: 8 bits, 256 virtual address spaces
On-chip multiplier
5-stage pipeline
(supports 68-/80-family interface)