HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 428

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

(b) Burst Write
Bank
D31–D0
(write)
Rev. 2.00 Feb. 12, 2010 Page 344 of 1330
REJ09B0554-0200
DACKn
(SA: IO → memory)
CKIO
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
BS
CKE
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
In a cycle of access to synchronous DRAM, the BS signal is asserted for one clock cycle at the
beginning of a bus cycle. When the data is accessed in the fill operation for a cache miss, the
32-bit boundary data including the missing data are first read, and then the 32-byte boundary
data including the missing data are read in wraparound mode.
Figure 10.32 is the timing chart for a burst-write operation with a burst length of 8. In this LSI,
a burst write takes place when a copy-back of the cache or a 32-byte transfer of data by the
DMAC occurs. In a burst-write operation, a WRITA command that performs auto precharging
is issued during the Tc1 cycle after the Tr cycle where the ACTV command is output. During
the write cycle, the write data is output simultaneously with the write command. For a write
command with an auto precharge, since precharging of the relevant bank in the synchronous
DRAM is performed after completion of the write command, no new command for the same
bank can be issued until precharging has been completed. As a result, besides the precharge
waiting cycle Tpc in read access, Trwl cycles are added to provide waiting time until
precharging starts after the write command has been issued, and these Trwl cycles delay the
issuing of new commands to the same bank. Bits TRWL2 to TRWL0 in MCR can be used to
select the number of Trwl cycles. The 32-byte boundary data is written in wraparound mode.
Figure 10.32 Basic Timing of a Burst Write to Synchronous DRAM
Tr
Row
Row
Row
Trw
Tc1
c1
Tc2
c2
H/L
c1
Tc3
c3
Tc4
c4
Tc5
c5
Tc6
c6
Tc7
c7
Tc8
c8
Trw1
Trw1
Tpc