HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 347

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
14
13
12
11
Bit
Name
HIZCNT
A0BST2
A0BST1
A0BST0
Initial
Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
High Impedance (High-Z) Control
Specifies the state of the RAS and CAS signals in
software standby mode and the bus-released state.
0: The RAS, WEn /DQMn, and RD/CASS/FRAME signals
1: The RAS, WEn /DQMn, and RD/CASS/FRAME signals
Area 0 Burst ROM Control
These bits specify whether burst ROM interface is used
in area 0. When burst ROM interface is used, they also
specify the number of accesses in a burst. When area 0
is used as an MPX interface area, the settings of these
bits are ignored.
000: Area 0 is accessed as SRAM interface.
001: Area 0 is accessed as burst ROM interface
010: Area 0 is accessed as burst ROM interface
011: Area 0 is accessed as burst ROM interface
100: Area 0 is accessed as burst ROM interface
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
made to the high-impedance in software standby
mode and the bus-released state
driven in software standby mode and the bus-released
state
(4 consecutive accesses). Can be used with 8-, 16-,
or 32-bit bus width
(8 consecutive accesses). Can be used with 8-, 16-,
or 32-bit bus width
(16 consecutive accesses). Can only be used with
8- or 16-bit bus width. The setting of 32-bit bus width
is prohibited.
(32 consecutive accesses). Can only be used with
8-bit bus width
Rev. 2.00 Feb. 12, 2010 Page 263 of 1330
REJ09B0554-0200