HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1385

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

B.
The MD8–MD0 pin values are input in the event of a power-on reset via the RESET pin.
Table B.1
Clock
Operating
Mode
0
1
2
3
4
6
Notes: 1. The multiplication factor of PLL1 is solely determined by the clock operating mode.
Table B.2
MD6
0
1
2. For the ranges input clock frequency, see the description of the EXTAL clock input
Mode Pin Settings
frequency (f
Signal Timing.
MD2
0
1
MD4
0
1
0
1
Pin Value
Clock Operating Modes (SH7760)
Area 0 Memory Map and Bus Width
Pin Combination
External
MD1
0
1
0
1
EX
MD3
0
1
0
1
0
1
0
1
) and the CKIO clock output (f
MD0
0
1
0
1
0
0
PLL1
On (×12) On
On (×12) On
On (×6)
On (×12) On
On (×6)
Off (×6)
Memory Type
Setting prohibited
Setting prohibited
Setting prohibited
MPX interface
Setting prohibited
SRAM interface
SRAM interface
SRAM interface
PLL2
On
On
Off
CPU
Clock
12
12
6
12
6
1
OP
) in section 33.3.1, Clock and Control
Rev. 2.00 Feb. 12, 2010 Page 1301 of 1330
(vs. Input Clock)
Bus
Clock
3
3/2
2
4
3
1/2
Frequency
Bus Width
Setting prohibited
Setting prohibited
Setting prohibited
32 bits
Setting prohibited
8 bits
16 bits
32 bits
Peripheral
Module Clock
3
3/2
1
2
3/2
1/2
REJ09B0554-0200
FRQCR
Initial Value
H'0E1A
H'0E2C
H'0E13
H'0E13
H'0E0A
H'0808