HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 602

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

14.2.4
CLKSTPCLR00 is a 32-bit write-only register that is used to clear corresponding bits in
CLKSTP00. Write 1 to the corresponding bits in CLKSTPCLR00 to restart supplying the clock.
Table 14.4 shows which module each bit is assigned to.
Initial value:
Initial value:
14.3
14.3.1
(1) Transition to Sleep Mode
If a SLEEP instruction is executed when the STBY bit in STBCR is cleared to 0, the chip switches
from the program execution state to sleep mode. After execution of the SLEEP instruction, the
CPU halts but its register contents are retained. The peripheral modules continue to operate, and
the clock continues to be output from the CKIO pin.
In sleep mode, a high-level signal is output at the STATUS1 pin, and a low-level signal at the
STATUS0 pin.
(2) Exit from Sleep Mode
Sleep mode is exited by means of an interrupt (NMI, IRL, IRQ, GPIO, or peripheral module) or a
reset.
In sleep mode, interrupts are accepted even if the BL bit in SR is 1. If necessary, SPC and SSR
should be saved to the stack before executing the SLEEP instruction.
(a) Exit by interrupt
(b) Exit by reset
Rev. 2.00 Feb. 12, 2010 Page 518 of 1330
REJ09B0554-0200
When an NMI, IRL, IRQ, GPIO, or peripheral module interrupt is generated, sleep mode is
exited and the interrupt exception handling is executed. The code corresponding to the
interrupt source is set in INTEVT.
Sleep mode is exited by means of a power-on or manual reset.
R/W:
R/W:
Bit:
Bit:
Clock Stop Clear Register 00 (CLKSTPCLR00)
Operation
Sleep Mode
31
15
W
W
0
0
30
14
W
W
0
0
29
13
W
W
0
0
28
12
W
W
0
0
27
11
W
W
0
0
26
10
W
W
0
0
25
W
W
0
9
0
24
W
W
0
8
0
23
W
W
0
7
0
22
W
W
0
0
6
21
W
W
0
5
0
20
W
W
0
4
0
19
W
W
0
3
0
18
W
W
0
2
0
17
W
W
0
1
0
16
W
W
0
0
0