HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 545

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

11.4.6
The conditions for ending DMA transfer are different for ending on individual channels and for
ending on all channels simultaneously. Following are the procedures for ending transfer, except
for ending transfer when the DMATCR value reaches 0.
1. Cycle steal mode (external request, on-chip peripheral module request, auto-request)
2. Burst mode, edge detection (external request, DMABRG request, on-chip peripheral module
3. Burst mode, level detection (external request)
4. Bus timing for transfer suspension
When transfer end conditions are met, the DMAC waits until all ongoing DMA transfers
requested before transfer end conditions are complete, and then stops the operation. In cycle
steal mode, the operation is the same for both edge and level transfer request detection.
request, auto-request)
It generates the same delay between the time transfer end conditions are met and the time the
DMAC stops the operation as in cycle steal mode. In burst mode with edge detection, only the
first transfer request activates the DMAC, but the timing of stop request (DE = 0 in CHCR,
DME = 0 in DMAOR) sampling is the same as the transfer request sampling timing shown in
Burst Mode, Single Address Mode, Edge Detection and Suspension of DMA Transfer with
DREQ Level Detection under Operation in section 11.4.5 (3) Operation. Therefore, a transfer
request is regarded as having been issued until a stop request is detected, and the
corresponding processing is executed before the DMAC stops.
It generates the same delay between the time transfer end conditions are met and the time the
DMAC stops the operation as in cycle steal mode. As in the case of burst mode with edge
detection, the timing of stop request (DE = 0 in CHCR, DME = 0 in DMAOR) sampling is the
same as the transfer request sampling timing shown in Burst Mode, Single Address Mode,
Edge Detection and Suspension of DMA Transfer in Case of DREQ Level Detection under
Operation in section 11.4.5 (3) Operation. Therefore, a transfer request is regarded as having
been issued until a stop request is detected, and the corresponding processing is executed
before the DMAC stops.
The DMAC suspends the operation after processing for one bus cycle unit is complete. In dual
address mode transfer, the DMAC executes write cycle processing even if a transfer end
condition is satisfied during the read cycle. It suspends the operation after completing the
transfers mentioned above in 1, 2, and 3.
Ending DMA Transfer
Rev. 2.00 Feb. 12, 2010 Page 461 of 1330
REJ09B0554-0200