HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 525

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

(3) Operation
• Cycle Steal Mode
• Burst Mode, Dual Address Mode, Level Detection
In cycle steal mode, The DREQ sampling timing differs for dual address mode and single
address mode, and for level detection and edge detection of DREQ.
For example, in figure 11.13 (external request 2-channel mode, cycle steal mode, dual address
mode, level detection), DMAC transfer begins, at the earliest, four CKIO cycles after the first
sampling operation. The second sampling operation is performed one cycle after the start of
the first DMAC transfer write cycle. If DREQ is not detected at this time, sampling is executed
in every subsequent cycle.
In figure 11.15 (external request 2-channel mode, cycle steal mode, dual address mode, edge
detection), DMAC transfer begins, at the earliest, five CKIO cycles after the first sampling
operation. The second sampling operation begins from the cycle in which the first DMAC
transfer read cycle ends. If DREQ is not detected at this time, sampling is executed in every
subsequent cycle.
For details of the timing for various types of memory access, see section 10, Bus State
Controller (BSC).
Figure 11.21 shows external request 2-channel mode, cycle steal mode, single address mode,
and level detection. In this case, too, transfer is started, at the earliest, four CKIO cycles after
the first DREQ sampling operation. The second sampling operation is performed one cycle
after the start of the first DMAC transfer bus cycle.
Figure 11.23 shows external request 2-channel mode, cycle steal mode, single address mode,
and edge detection. In this case, transfer is started, at the earliest, five CKIO cycles after the
first DREQ sampling operation. The second sampling begins one cycle after the first assertion
of DRAK.
In single address mode, the DACK signal is output every DMAC transfer cycle.
DREQ sampling timing in burst mode using dual address mode and level detection is virtually
the same as for cycle steal mode.
For example, in figure 11.17, DMAC transfer begins, at the earliest, four CKIO cycles after the
first sampling operation. The second sampling operation is performed one cycle after the start
of the first DMAC transfer write cycle.
In the case of dual address mode transfer initiated by an external request, the DACK signal can
be output in either the read cycle or the write cycle of the DMAC transfer according to the
specification of the AM bit in CHCR.
Rev. 2.00 Feb. 12, 2010 Page 441 of 1330
REJ09B0554-0200