HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 919

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

• CANMBIMR0
Initial value:
22.5.14 Unread Message Status Registers 1 and 0 (CANUMSR1, CANUMSR0)
The CANUMSR are two 16-bit read/write registers and record any receive mailboxes that have
been emptied prior to a new message received. If the host CPU has not cleared the corresponding
bit in CANRXPR or CANRFPR when a new message for that mailbox is received, the
corresponding CANUMSR bit is set to 1. This bit may be cleared by writing a 1 to the
corresponding bit location in the CANUMSR. Writing a 0 has no effect.
If a mailbox is configured as a transmit box, the corresponding CANUMSR bit will not be set.
• CANUMSR1
Initial value:
15 to 0
Bit
15 to 0
Bit
R/W:
R/W:
Bit:
Bit:
UMSR1
MBIMR1[15:0]
MBIMR0
Bit Name
MBIMR0[15:0]
R/W
R/W
_15
_15
15
15
1
0
Bit Name
UMSR1
MBIMR0
R/W
R/W
_14
_14
14
14
1
0
UMSR1
MBIMR0
R/W
R/W
_13
13
_13
13
1
0
UMSR1
MBIMR0
All 1
R/W
Initial Value
All 1
R/W
_12
Initial Value
12
12
_12
1
0
MBIMR0
UMSR1
R/W
R/W
_11
_11
11
11
1
0
MBIMR0
UMSR1
R/W
R/W
_10
_10
10
10
1
0
R/W
R/W
R/W
UMSR1
MBIMR0
R/W
R/W
R/W
_9
_9
9
1
9
0
UMSR1
MBIMR0
R/W
R/W
_8
_8
8
1
8
0
Enable or disable interrupt requests from
individual Mailboxes 31 to 16 respectively.
0: Interrupt requests from IRR1/IRR2/IRR8/
1: Interrupt requests from IRR1/IRR2/IRR8/
Description
Enable or disable interrupt requests from
individual Mailboxes 15 to 0 respectively.
0: Interrupt requests from IRR1/IRR2/IRR8/
1: Interrupt requests from IRR1/IRR2/IRR8/
UMSR1
MBIMR0
IRR9 enabled.
IRR9 disabled.
IRR9 enabled.
IRR9 disabled.
R/W
R/W
_7
_7
1
0
7
7
UMSR1
Rev. 2.00 Feb. 12, 2010 Page 835 of 1330
MBIMR0
R/W
R/W
_6
_6
6
1
6
0
UMSR1
MBIMR0
R/W
R/W
_5
_5
5
1
5
0
Description
UMSR1
MBIMR0
R/W
R/W
_4
_4
4
1
4
0
UMSR1
MBIMR0
R/W
R/W
_3
3
_3
1
3
0
REJ09B0554-0200
MBIMR0
UMSR1
R/W
R/W
_2
_2
2
1
2
0
MBIMR0
UMSR1
R/W
R/W
_1
_1
1
1
1
0
UMSR1
MBIMR0
R/W
R/W
_0
_0
0
1
0
0