HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 30

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Item
29.4.2 Multi Mode
29.4.5 External
Trigger Input Timing
29.7.5 Notice of the
DMA transmission of
A/D converter
29.7.6 Notice of Scan
mode and Multi mode
of A/D conversion
29.7.7 Notice of Multi
mode of A/D conversion
30.3 Register
Configuration
Table 30.2 Register
Configuration (1)
Rev. 2.00 Feb. 12, 2010 Page xxviii of lxxxii
REJ09B0554-0200
Page
1049
1055
1059
1060,
1061
1061
1065
1066
Revision (See Manual for Details)
Description amended
1. When the ADST bit in ADCSR is set to 1 by software,
Description amended
A/D conversion can also be started by an external trigger input
(except in multi mode)….
Newly added
Newly added
Newly added
Table amended
Register Name
LCDC input clock register
LCDC module type register
LCDC data format register
LCDC scan mode register
LCDC display start address
register - upper
LCDC display start address
register - lower
LCDC display line address offset
register
LCDC palette control register
Palette data registers 00 to FF
LCDC horizontal character
number register
LCDC horizontal synchronization
signal register
LCDC vertical display line number
register
LCDC vertical total line number
register
LCDC vertical synchronization
signal register
LCDC AC modulation signal
toggle line number register
LCDC interrupt control register
LCDC power management mode
register
Register Name
LCDC power supply sequence
period register
LCDC control register
conversion starts with the first channel (AN0).
Abbrev.
LDICKR
LDMTR
LDDFR
LDSMR
LDSARU
LDSARL
LDLAOR
LDPALCR R/W H'FE30 0C12 H'1E30 0C12 16
LDPR00 to
FF*
LDHCNR
LDHSYNR R/W H'FE30 0C16 H'1E30 0C16 16
LDVDLNR R/W H'FE30 0C18 H'1E30 0C18 16
LDVTLNR
LDVSYNR R/W H'FE30 0C1C H'1E30 0C1C 16
LDACLNR R/W H'FE30 0C1E H'1E30 0C1E 16
LDINTR
LDPMMR
Abbrev.
LDPSPR
LDCNTR
1
R/W H'FE30 0C0C H'1E30 0C0C 32
R/W P4 Address
R/W H'FE30 0C00 H'1E30 0C00 16
R/W H'FE30 0C02 H'1E30 0C02 16
R/W H'FE30 0C04 H'1E30 0C04 16
R/W H'FE30 0C06 H'1E30 0C06 16
R/W H'FE30 0C08 H'1E30 0C08 32
R/W H'FE30 0C10 H'1E30 0C10 16
R/W H'FE30 0800
R/W H'FE30 0C14 H'1E30 0C14 16
R/W H'FE30 0C1A H'1E30 0C1A 16
R/W H'FE30 0C20 H'1E30 0C20 16
R/W H'FE30 0C24 H'1E30 0C24 16
R/W P4 Address
R/W H'FE30 0C26 H'1E30 0C26 16
R/W H'FE30 0C28 H'1E30 0C28 16
Area 7
Address
H'1E30 0800 32
Area 7
Address
Size
Size
Pck
Pck
Pck
Pck
Sync
Clock
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Sync
Clock
Pck
Pck
Modification
During
Display*
No
No
No
No
Yes
Yes
Yes
No
Yes
No
No
No
No
No
Yes
No
No
Modification
During
Display*
No
No
A/D
2
2