HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 929

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

22.6.4
The diagram below shows the message receive sequence.
Loop (N=31(15) ; N > 0 ; N=N-1)
HCAN2
Note: * Please confirm CANUMSR[N] = 0 when NMC[N] = 1
• Store message by
• Set CANUMSR
• Set IRR9 (if MBIMR[N]=0)
• Generate interrupt signal
and go back to the idle state
overwriting
(if IMR9=0)
Store mailbox-number[N]
(if MBC is set to receive)
Valid CAN-ID received
Mailbox[N] + LAFM[N]
interrupt signal
matched?
Compare ID with
Message Reception Sequence
ID
Yes
No
End of arbitration Field
N=0?
N=N-1
• Reject message
• Set CANUMSR
• Set IRR9 (if MBIMR[N]=0)
• Generate interrupt signal
Figure 22.8 Message Receive Sequence
(if IMR9=0)
No
interrupt signal
Overwrite
Yes
Idle
CPU received interrupt
Overrun
Valid CAN frame received
(RFPR[N]) already
MSG overwrite
LAFM/CAN-ID
Check MBC/
or overrun?
End of frame
RXPR[N]
(NMC)
set?
• Store message
• Set RXPR[N] (RFPR[N])
• Set IRR1
• Generate interrupt signal
(IRR2) (if MBIMR[N]=0)
interrupt signal
Correct
(if IMR1(IMR2)=0)
Yes
Rev. 2.00 Feb. 12, 2010 Page 845 of 1330
Incorrect
No
CAN bus
Write a 1 to RXPR[N]
Read RXPR[N]=0
Read Mailbox[N]*
Read RXPR[N]=1
Read IRR1=0
IRR1 set to 1?
Read IRR
REJ09B0554-0200
Yes
No