HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 573

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 12 Clock Pulse Generator (CPG)
(2) PLL Circuit 2
PLL circuit 2 coordinates the phases of the bus clock and the clock signal output from the CKIO
pin. Starting and stopping of this circuit is controlled by the setting of the frequency control
register.
(3) PLL Circuit 3
PLL circuit 3 coordinates the phases of the bus clock and the clock signal output from the DCK
pin. Starting and stopping of this circuit is controlled by the setting of the clock division register.
(4) Crystal Oscillator
Oscillation circuits for when a crystal resonator is connected to the XTAL and EXTAL pins.
Usage of the crystal oscillator is enabled by the MD8 pin setting.
(5) Frequency Divider 1
Frequency divider 1 generates the CPU clock (Ick), bus clock (Bck), and peripheral clock (Pck).
The division ratio is set in the frequency control register.
(6) Frequency Divider 2
Frequency divider 2 generates the clock output from the DCK pin. The division ratio is set in the
clock division register.
(7) Frequency Divider 3
(Frequency divider 3 generates the module clock (Fck). The division ratio is set in the module
clock control register.
(8) Clock Frequency Control Circuit
The clock frequency control circuit controls the clock frequency by means of the MD pins,
frequency control register, clock division register, and module clock control register.
(9) Standby Control Circuit
The standby control circuit controls the state of the on-chip oscillation circuits and other modules
when the clock is switched or in sleep and standby modes.
(10) Frequency Control Register (FRQCR)
FRQCR contains control bits for the clock output from the CKIO pin, on/off of PLL circuits 1 and
2, and frequency division ratios of the CPU clock, bus clock, and peripheral clock.
Rev. 2.00 Feb. 12, 2010 Page 489 of 1330
REJ09B0554-0200