HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 671

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
15 to 8
7
Bit Name
—
ER
Initial Value
All 0
0
R/W
R
R/W*
1
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Receive Error
Indicates that a framing error or parity error
occurred during reception. The ER flag is not
affected and retains its previous state when the
RE bit in SCSCR is cleared to 0. When a receive
error occurs, the receive data is still transferred to
SCFRDR, and reception continues.
The FER and PER bits in SCFSR can be used to
determine whether there is a receive error in the
readout data from SCFRDR.
0: No framing error or parity error occurred during
reception
[Clearing conditions]
•
•
1: A framing error or parity error occurred during
reception
[Setting conditions]
•
• When, in reception, the number of 1-bits in the
Power-on reset or manual reset
When the SCIF checks whether the stop bit at
the end of the receive data is 1 when
reception ends, and the stop bit is 0*
receive data plus the parity bit does not match
the parity setting (even or odd) specified by
the O/E bit in SCSMR
When 0 is written to ER after reading ER = 1
Rev. 2.00 Feb. 12, 2010 Page 587 of 1330
REJ09B0554-0200
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