HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 705

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

(6) Simultaneous Serial Data Transmission and Reception (Synchronous Mode)
Figure 17.21 shows a sample flowchart for simultaneous serial data transmission and reception.
Use the following procedure for simultaneous serial transmission and reception after enabling the
SCIF for both transmission and reception.
Figure 17.21 Sample Simultaneous Serial Transmission and Reception Flowchart
No
No
No
Start of transmission and reception
End of transmission and reception
Write transmit data to SCFTDR,
Read ORER flag in SCLSR
Read TDFE flag in SCFSR
Read RDF flag in SCFSR
SCFRDR, and clear RDF
Clear TE and RE bits
and clear TDFE flag
Read receive data in
flag in SCFSR to 0
All data received?
in SCSCR to 0
in SCFSR to 0
Initialization
ORER = 1?
TDFE = 1?
RDF = 1?
Yes
No
Yes
Yes
Error handling
[4]
[5]
[1]
[2]
Yes
[3]
Note:
[1] SCIF initialization:
[2] SCIF status check and transmit data
[3] Receive error handling:
[4] SCIF status check and receive data
[5] Serial transmission and reception
See Sample SCIF Initialization
Read SCFSR and check that the
To continue serial transmission and
Flowchart in figure 17.16.
write:
TDFE flag is set to 1, then write
transmit data to SCFTDR, and clear
the TDFE flag to 0. The transition of
the TDFE flag from 0 to 1 can also be
identified by a TXI interrupt.
identify any error, perform the
appropriate error handling, then clear
the ORER flag to 0. Reception cannot
be resumed while the ORER flag is
set to 1.
read:
1, then read the receive data in
SCFRDR, and clear the RDF flag to
0. The transition of the RDF flag from
0 to 1 can also be identified by an RXI
interrupt.
continuation procedure:
reception, read RDF flag and
SCFRDR, and clear the RDF flag to 0
before receiving the MSB in the
current frame. Similarly, read 1 from
the TDFE flag to confirm that writing
is possible before transmitting the
MSB in the current frame. Then write
data to SCFTDR and clear the TDFE
flag to 0.
Read the ORER flag in SCLSR to
Read SCFSR and check that RDF =
When switching from a transmit operation
or receive operation to simultaneous
transmission and reception operations,
clear the TE and RE bits to 0, and then
set them simultaneously to 1.
Rev. 2.00 Feb. 12, 2010 Page 621 of 1330
REJ09B0554-0200