HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 568

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

11.6.14 DMABRG Interrupts
The DMABRG issues three interrupts: a USB address error interrupt, an all data transfer end
interrupt, and a half data transfer end interrupt. The DMABRG generates a USB address error
interrupt request for a DMA transfer request from the USB, an all data transfer end interrupt
request for a DMA transfer request from the HAC, SSI, or USB, and a half data transfer end
interrupt request for a transfer request from the HAC or SSI. A DMABRG interrupt request is not
generated for a DMA transfer request from the LCDC. When a reset is cancelled, the interrupt
priority is in the following order: a USB address error interrupt, an all data transfer end interrupt,
and a half data transfer end interrupt.
(1) USB Address Error Interrupt Request (DMABRGI0)
When a USB address error occurs with the UAE bit in DMABRGCR set to 1, the DMABRG sets
the UAF bit in DMABRGCR to 1 and outputs an interrupt request to the INTC.
(2) All Data Transfer End Interrupt Request (DMABRGI1)
• When all data transfer is completed on the receive side for channel 1 of the HAC or SSI with
• When all data transfer is completed on the transmit side for channel 1 of the HAC or SSI with
• When all data transfer is completed on the receive side for channel 0 of the HAC or SSI with
• When all data transfer is completed on the transmit side for channel 0 of the HAC or SSI with
• When USB data transfer is completed with the UTE bit in DMABRGCR set to 1, the
(3) Half Data Transfer End Interrupt Request (DMABRGI2)
• When data transfer of half of the bytes specified in DMAARXTCR is completed on the receive
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the A1RXEE bit in DMABRGCR set to 1, the DMABRG sets the A1RXEF bit in
DMABRGCR to 1 and outputs an interrupt request to the INTC.
the A1TXEE bit in DMABRGCR set to 1, the DMABRG sets the A1TXEF bit in
DMABRGCR to 1 and outputs an interrupt request to the INTC.
the A0RXEE bit in DMABRGCR set to 1, the A0RXEF bit in DMABRGCR is set to 1 and an
interrupt request is output to the INTC.
the A0TXEE bit in DMABRGCR set to 1, the DMABRG sets the A0TXEF bit in
DMABRGCR to 1 and outputs an interrupt request to the INTC.
DMABRG sets the UTF bit in DMABRGCR to 1 and outputs an interrupt request to the INTC.
side for channel 1 of the HAC or SSI with the A1RXHE bit in DMABRGCR set to 1, the
DMABRG sets the A1RXHF bit in DMABRGCR to 1 and outputs an interrupt request to the
INTC.