HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 770

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 19 I
Notes: 1. ICRXD is a 16-byte FIFO register. When RDF = 1, it is possible to read data of at least
19.3.13 FIFO Interrupt Enable Register (ICFIER)
ICFIER is a register that enables or disables interrupt request from the FIFO operation source.
ICFIER can always be read from and written to by the CPU.
Initial value:
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 686 of 1330
REJ09B0554-0200
Bit
31 to 3
2
1
R/W:
R/W:
Bit:
Bit:
2. ICTXD is a 16-byte FIFO register. When TDFE = 1, the maximum byte count that can
Bit Name
⎯
TEIE
RXIE
the receive trigger byte count. Reading empty ICRXD will return an undefined value.
The receive byte count in ICRXD is indicated by ICRFDR.
be written to ICTXD is 16 minus the transmit trigger byte count. If the written byte count
exceeds the maximum, the excess data is ignored. The byte count in ICTXD is
indicated by ICTFDR.
31
15
2
R
R
0
0
-
-
C Bus Interface
30
14
-
R
-
R
0
0
29
13
R
R
0
0
-
-
Initial Value
All 0
0
0
28
12
R
R
0
0
-
-
27
11
R
R
0
0
-
-
R/W
R
R/W
R/W
26
10
R
R
0
0
-
-
25
R
R
-
0
9
-
0
Description
Reserved.
These bits are always read as 0, and the write
value should always be 0.
Transmit End Interrupt Enable
Enables or disables the generation of the transmit
end interrupt (TEI) when the TEND flag of ICFSR
is set to 1.
0: The transmit end interrupt (TEI) is disabled
1: The transmit end interrupt (TEI) is enabled
Receive Interrupt Enable
Enables or disables the generation of the receive
data full interrupt (RXI) when the RDF flag of
ICFSR is set to 1.
0: The receive data full interrupt (RXI) is disabled
1: The receive data full interrupt (RXI) is enabled
24
R
R
0
8
0
-
-
23
R
R
0
7
0
-
-
22
R
R
0
6
0
-
-
21
R
R
0
5
0
-
-
20
R
R
0
4
0
-
-
19
R
R
0
3
0
-
-
TEIE RXIE TXIE
R/W
18
R
0
2
0
-
R/W
17
R
0
1
0
-
R/W
16
R
0
0
0
-