HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 477

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
24
23 to 20 ⎯
19
18
Bit Name
DTC
DS
RL
Initial Value R/W
0
All 0
0
0
R/W
R
R/W
R/W
Description
Destination Address Wait Control Select
Specifies the CS5 or CS6 space wait cycle control
for the destination address when accessing a
PCMCIA interface area.
0: CS5 space wait cycle selection
1: CS6 space wait cycle selection
Reserved
These bits are always read as 0. The write value
should always be 0.
DREQ Select
Specifies either low level detection or falling edge
detection as the sampling method for the DREQ pin.
In external request 2-channel mode, this bit is valid
only in CHCR0 and CHCR1.
In DMABRG mode, this bit is valid in CHCR0 to
CHCR7 and each of bits DS3 to DS0 in DMARCR
should be specified to the same as this bit.
0: Low level detection
1: Falling edge detection
Level detection burst mode when TM = 1 and DS = 0
Edge detection burst mode when TM = 1 and DS = 1
Request Check Level
Selects whether the DRAK signal that notifies an
external device of the acceptance of DREQ is an
active-high or active-low output.
In external request 2-channel mode, this bit is valid
only in CHCR0 and CHCR1.
In DMABRG mode, this bit is invalid and the DRAK
polarity is specified by bits RL3 to RL0 in DMARCR.
0: DRAK is an active-high output
1: DRAK is an active-low output
Settings of bits A5W2 to A5W0 in WCR2 and bits
A5PCW1 and A5PCW0, A5TED2 to A5TED0, and
A5TEH2 to A5TEH0 in PCR are selected
Settings of bits A6W2 to A6W0 in WCR2 and bits
A6PCW1 and A6PCW0, A6TED2 to A6TED0, and
A6TEH2 to A6TEH0 in PCR are selected
Rev. 2.00 Feb. 12, 2010 Page 393 of 1330
REJ09B0554-0200