HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 903

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
12
11, 10
9
Bit Name
IRR12
⎯
IRR9
Initial Value
0
All 0
0
R/W
R/W
R
R/W
Description
Wake-up on Bus Activity
Indicates that a CAN bus activity is present. When
the HCAN is in sleep mode and a recessive to
dominant bit transition takes place on the CAN
bus, this bit is set. The operation of this interrupt
is configured in the Master Control Register.
(MCR7 – Auto-wake Mode). This interrupt is
cleared by writing a 1 to this bit position. Writing a
0 has no effect.
0: Bus idle state
1: CAN bus activity is detected in HCAN2 sleep
Reserved
The write value should always be 0. The read
value is not guaranteed.
Message Overrun/Overwrite Interrupt Flag
Indicates that a message has been received but
the existing message in the matching Mailbox has
not been read due to the corresponding
CANRXPR or CANRFPR set to 1. The received
message is either abandoned (overrun) or
overwritten depeding on the value of the NMC
(New Message Control) bit. This bit is cleared by
writing a 1 to the correspondent bit position in
CANUMSR (Unread Message Status Register).
Writing a 0 has no effect.
0: No message overrun/overwrite
1: Receive message overrun and its storage has
Clearing condition: Clean all bits in CANUMSR.
been rejected or message overwrite.
Setting condition: Message is received while
the corresponding CANRXPR or CANRFPR =1
and CANMBIMR = 0.
Clearing condition: Write a 1 to this bit.
mode.
Setting condition: Bit transition, from recessive
to dominant, is detected in sleep mode.
Rev. 2.00 Feb. 12, 2010 Page 819 of 1330
REJ09B0554-0200