HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 793

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

20.3
The SSI module has the following registers. As for addresses of these registers and register status
in each processing state, see section 32 List of Registers. Note that the initial value of SSISR is
determined depending on the settings of the SCKD and CKDV bits in SSICR after the clock is
supplied. Distinction with channels is omitted for the description of this document.
Table 20.2 Register Configuration (1)
Ch.
0
1
Table 20.2 Register Configuration (2)
Ch.
0
1
Notes: 1. Bits 27 and 26 allow a write of 0 only to clear the flag.
Control register 0
Status register 0
Transmit data register 0
Receive data register 0
Control register 1
Status register 1
Transmit data register 1
Receive data register 1
Register Name
Register Name
Control register 0
Status register 0
Transmit data register 0
Receive data register 0
Control register 1
Status register 1
Transmit data register 1
Receive data register 1
2. When exiting hardware standby mode, this module is entered in the power-on reset
Register Descriptions
state by the RESET pin.
SSICR0
SSISR0
SSITDR0
SSIRDR0 H'0000 0000 H'0000 0000 Retained
SSICR1
SSISR1
SSITDR1
SSIRDR1 H'0000 0000 H'0000 0000 Retained
Abbrev.
Abbrev.
SSICR0
SSISR0
SSITDR0
SSIRDR0
SSICR1
SSISR1
SSITDR1
SSIRDR1
H'0000 0000 H'0000 0000 Retained
H'0200 0003 H'0200 0003 Retained
H'0000 0000 H'0000 0000 Retained
H'0000 0000 H'0000 0000 Retained
H'0200 0003 H'0200 0003 Retained
H'0000 0000 H'0000 0000 Retained
Power-on
Reset by
RESET
Pin/WDT/
H-UDI
R/W
R/W
R/W*
R/W
R
R/W
R/W*
R/W
R
1
1
P4 Address
H'FE68 0000
H'FE68 0004
H'FE68 0008
H'FE68 000C
H'FE69 0000
H'FE69 0004
H'FE69 0008
H'FE69 000C
Manual Reset
by RESET
Pin/WDT/
Multiple
Exception
Rev. 2.00 Feb. 12, 2010 Page 709 of 1330
Sleep
by Sleep
Instruction/
Deep Sleep
Area 7 Address
H'1E68 0000
H'1E68 0004
H'1E68 0008
H'1E68 000C
H'1E69 0000
H'1E69 0004
H'1E69 0008
H'1E69 000C
by
Hardware
REJ09B0554-0200
*
2
Standby
Size
32
32
32
32
32
32
32
32
by Software/
Each
Module
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Sync
Clock
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck