HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 753

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
31 to 7
6
5
4
3
Bit Name
⎯
GCAR
STM
SSR
SDE
Initial Value
All 0
0
0
0
0
R
R/W
R
R
R/W*
R/W*
Description
Reserved
These bits are always read as 0, and the write
value should always be 0.
General Call Address Received
Indicates that the address received from the bus
is a general call address (00H). This bit does not
cause an interrupt.
This bit is automatically cleared to 0 by hardware
when the SIE bit (bit 2 in the slave control
register) is 0 or when the SSR bit (bit 4 in the
slave status register) is set to 1.
Slave Transmit Mode
Current slave transmit mode (read or write).
Setting this bit to 1 indicates a write operation,
and clearing this bit to 0 indicates a read. This
status bit does not cause an interrupt.
This bit is automatically cleared by hardware
when the SIE bit (bit 2 in the slave control
register) is 0 or when the SSR bit (bit 4 in the
slave status register) is set to 1.
Slave Stop Received
A stop has been output to the bus. This status bit
becomes active after the rising edge of SDA
during the stop bit.
Slave Data Empty
Transmit data has been loaded into the shift
register. At the start of data byte transmission, the
contents of the ICTXD register are loaded into a
shift register ready for the data to be passed onto
the bus. This status bit indicates that this has
taken place and that the ICTXD register is again
ready to receive further data. This status bit
becomes active on the falling edge of SCL before
the first data bit. In the single buffer mode, this bit
must be reset each time a new data has been
written to the ICTXD register. This is because the
slave holds SCL low to stall the bus, if it reaches
the start of a slave transmit cycle and this status
bit is still set. In the FIFO buffer mode, this bit is
not used.
Rev. 2.00 Feb. 12, 2010 Page 669 of 1330
Section 19 I
REJ09B0554-0200
2
C Bus Interface